Commit c334f9c8 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host-altera', 'pci/host-imx6', 'pci/host-keystone',... 

Merge branches 'pci/host-altera', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-rcar', 'pci/host-tegra', 'pci/host-thunder', 'pci/host-vmd', 'pci/host-xilinx' and 'pci/host-xilinx-nwl' into next

* pci/host-altera:
  PCI: altera: Fix altera_pcie_link_is_up()

* pci/host-imx6:
  PCI: imx6: Add DT bindings to configure PHY Tx driver settings

* pci/host-keystone:
  PCI: keystone: Defer probing if devm_phy_get() returns -EPROBE_DEFER

* pci/host-rcar:
  PCI: rcar: Depend on ARCH_RENESAS, not ARCH_SHMOBILE

* pci/host-tegra:
  PCI: tegra: Remove misleading PHYS_OFFSET
  PCI: tegra: Track bus -> CPU mapping
  PCI: tegra: Remove unused struct tegra_pcie.num_ports field
  PCI: tegra: Implement ->{add,remove}_bus() callbacks
  PCI: Add pci_ops.{add,remove}_bus() callbacks

* pci/host-thunder:
  PCI: thunder: Add driver for ThunderX-pass{1,2} on-chip devices
  PCI: thunder: Add PCIe host driver for ThunderX processors
  PCI: generic: Expose pci_host_common_probe() for use by other drivers
  PCI: generic: Add pci_host_common_probe(), based on gen_pci_probe()
  PCI: generic: Move structure definitions to separate header file

* pci/host-vmd:
  x86/PCI: VMD: Attach VMD resources to parent domain's resource tree
  x86/PCI: VMD: Set bus resource start to 0
  x86/PCI: VMD: Document code for maintainability

* pci/host-xilinx:
  microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver
  PCI: xilinx: Update Zynq binding with Microblaze node
  PCI: xilinx: Don't call pci_fixup_irqs() on Microblaze
  PCI: xilinx: Remove dependency on ARM-specific struct hw_pci
  PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT

* pci/host-xilinx-nwl:
  PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller
parents 18e5e691 eff31f40 28e3abe5 25de15c9 304e6d57 e32faa30 7b6e7ba8 2c2c5c5c 01cf9d52 ab597d35

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

+7 −0
Original line number Diff line number Diff line
@@ -13,6 +13,13 @@ Required properties: 
- clock-names: Must include the following additional entries:

	- "pcie_phy"



Optional properties:

- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0

- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0

- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20

- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127

- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127



Example:



	pcie@0x01000000 {

Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt

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* ThunderX PCI host controller for pass-1.x silicon



Firmware-initialized PCI host controller to on-chip devices found on

some Cavium ThunderX processors.  These devices have ECAM-based config

access, but the BARs are all at fixed addresses.  We handle the fixed

addresses by synthesizing Enhanced Allocation (EA) capabilities for

these devices.



The properties and their meanings are identical to those described in

host-generic-pci.txt except as listed below.



Properties of the host controller node that differ from

host-generic-pci.txt:



- compatible     : Must be "cavium,pci-host-thunder-ecam"



Example:



	pcie@84b000000000 {

		compatible = "cavium,pci-host-thunder-ecam";

		device_type = "pci";

		msi-parent = <&its>;

		msi-map = <0 &its 0x30000 0x10000>;

		bus-range = <0 31>;

		#size-cells = <2>;

		#address-cells = <3>;

		#stream-id-cells = <1>;

		reg = <0x84b0 0x00000000 0 0x02000000>;  /* Configuration space */

		ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */

	};

Documentation/devicetree/bindings/pci/pci-thunder-pem.txt

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* ThunderX PEM PCIe host controller



Firmware-initialized PCI host controller found on some Cavium

ThunderX processors.



The properties and their meanings are identical to those described in

host-generic-pci.txt except as listed below.



Properties of the host controller node that differ from

host-generic-pci.txt:



- compatible     : Must be "cavium,pci-host-thunder-pem"



- reg            : Two entries: First the configuration space for down

                   stream devices base address and size, as accessed

                   from the parent bus. Second, the register bank of

                   the PEM device PCIe bridge.



Example:



    pci@87e0,c2000000 {

	compatible = "cavium,pci-host-thunder-pem";

	device_type = "pci";

	msi-parent = <&its>;

	msi-map = <0 &its 0x10000 0x10000>;

	bus-range = <0x8f 0xc7>;

	#size-cells = <2>;

	#address-cells = <3>;



	reg = <0x8880 0x8f000000 0x0 0x39000000>,  /* Configuration space */

	      <0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */

	ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */

		 <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */

		 <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */

		 <0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */



	#interrupt-cells = <1>;

	interrupt-map-mask = <0 0 0 7>;

	interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */

			<0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */

			<0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */

			<0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */

    };

Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt

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* Xilinx NWL PCIe Root Port Bridge DT description



Required properties:

- compatible: Should contain "xlnx,nwl-pcie-2.11"

- #address-cells: Address representation for root ports, set to <3>

- #size-cells: Size representation for root ports, set to <2>

- #interrupt-cells: specifies the number of cells needed to encode an

	interrupt source. The value must be 1.

- reg: Should contain Bridge, PCIe Controller registers location,

	configuration space, and length

- reg-names: Must include the following entries:

	"breg": bridge registers

	"pcireg": PCIe controller registers

	"cfg": configuration space region

- device_type: must be "pci"

- interrupts: Should contain NWL PCIe interrupt

- interrupt-names: Must include the following entries:

	"msi1, msi0": interrupt asserted when MSI is received

	"intx": interrupt asserted when a legacy interrupt is received

	"misc": interrupt asserted when miscellaneous is received

- interrupt-map-mask and interrupt-map: standard PCI properties to define the

	mapping of the PCI interface to interrupt numbers.

- ranges: ranges for the PCI memory regions (I/O space region is not

	supported by hardware)

	Please refer to the standard PCI bus binding document for a more

	detailed explanation

- msi-controller: indicates that this is MSI controller node

- msi-parent:  MSI parent of the root complex itself

- legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts

	- interrupt-controller: identifies the node as an interrupt controller

	- #interrupt-cells: should be set to 1

	- #address-cells: specifies the number of cells needed to encode an

		address. The value must be 0.





Example:

++++++++



nwl_pcie: pcie@fd0e0000 {

	#address-cells = <3>;

	#size-cells = <2>;

	compatible = "xlnx,nwl-pcie-2.11";

	#interrupt-cells = <1>;

	msi-controller;

	device_type = "pci";

	interrupt-parent = <&gic>;

	interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;

	interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";

	interrupt-map-mask = <0x0 0x0 0x0 0x7>;

	interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,

			<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,

			<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,

			<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;



	msi-parent = <&nwl_pcie>;

	reg = <0x0 0xfd0e0000 0x0 0x1000>,

	      <0x0 0xfd480000 0x0 0x1000>,

	      <0x0 0xe0000000 0x0 0x1000000>;

	reg-names = "breg", "pcireg", "cfg";

	ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;



	pcie_intc: legacy-interrupt-controller {

		interrupt-controller;

		#address-cells = <0>;

		#interrupt-cells = <1>;

	};



};

Documentation/devicetree/bindings/pci/xilinx-pcie.txt

+29 −3
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ Required properties: 
	Please refer to the standard PCI bus binding document for a more

	detailed explanation



Optional properties:

Optional properties for Zynq/Microblaze:

- bus-range: PCI bus numbers covered



Interrupt controller child node
@@ -38,13 +38,13 @@ the four INTx interrupts in ISR and route them to this domain. 


Example:

++++++++



Zynq:

	pci_express: axi-pcie@50000000 {

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		compatible = "xlnx,axi-pcie-host-1.00.a";

		reg = < 0x50000000 0x10000000 >;

		reg = < 0x50000000 0x1000000 >;

		device_type = "pci";

		interrupts = < 0 52 4 >;

		interrupt-map-mask = <0 0 0 7>;
@@ -60,3 +60,29 @@ Example: 
			#interrupt-cells = <1>;

		};

	};





Microblaze:

	pci_express: axi-pcie@10000000 {

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		compatible = "xlnx,axi-pcie-host-1.00.a";

		reg = <0x10000000 0x4000000>;

		device_type = "pci";

		interrupt-parent = <&microblaze_0_intc>;

		interrupts = <1 2>;

		interrupt-map-mask = <0 0 0 7>;

		interrupt-map = <0 0 0 1 &pcie_intc 1>,

				<0 0 0 2 &pcie_intc 2>,

				<0 0 0 3 &pcie_intc 3>,

				<0 0 0 4 &pcie_intc 4>;

		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;



		pcie_intc: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};



	};

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