Commit c30cb8f0 authored by Andre Przywara's avatar Andre Przywara Committed by David S. Miller
Browse files

net: axienet: Drop MDIO interrupt registers from ethtools dump 



Newer revisions of the IP don't have these registers. Since we don't
really use them, just drop them from the ethtools dump.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d6349e3e

drivers/net/ethernet/xilinx/xilinx_axienet.h

+0 −7
Original line number Diff line number Diff line
@@ -165,13 +165,6 @@ 
#define XAE_MDIO_MCR_OFFSET	0x00000504 /* MII Management Control */

#define XAE_MDIO_MWD_OFFSET	0x00000508 /* MII Management Write Data */

#define XAE_MDIO_MRD_OFFSET	0x0000050C /* MII Management Read Data */

#define XAE_MDIO_MIS_OFFSET	0x00000600 /* MII Management Interrupt Status */

/* MII Mgmt Interrupt Pending register offset */

#define XAE_MDIO_MIP_OFFSET	0x00000620

/* MII Management Interrupt Enable register offset */

#define XAE_MDIO_MIE_OFFSET	0x00000640

/* MII Management Interrupt Clear register offset. */

#define XAE_MDIO_MIC_OFFSET	0x00000660

#define XAE_UAW0_OFFSET		0x00000700 /* Unicast address word 0 */

#define XAE_UAW1_OFFSET		0x00000704 /* Unicast address word 1 */

#define XAE_FMI_OFFSET		0x00000708 /* Filter Mask Index */

drivers/net/ethernet/xilinx/xilinx_axienet_main.c

+0 −4
Original line number Diff line number Diff line
@@ -1258,10 +1258,6 @@ static void axienet_ethtools_get_regs(struct net_device *ndev, 
	data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);

	data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);

	data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);

	data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);

	data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);

	data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);

	data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);

	data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);

	data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);

	data[29] = axienet_ior(lp, XAE_FMI_OFFSET);

CRA Git | Maintained and supported by SUSTech CRA and CCSE