Commit c2fd8756 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Stephen Boyd
Browse files

clk: uniphier: add ethernet clock control support for PXs3 



Add clock control for ethernet controller on PXs3 SoC.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent afeb079b

drivers/clk/uniphier/clk-uniphier-sys.c

+2 −0
Original line number Diff line number Diff line
@@ -244,6 +244,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { 
	UNIPHIER_LD20_SYS_CLK_SD,

	UNIPHIER_LD11_SYS_CLK_NAND(2),

	UNIPHIER_LD11_SYS_CLK_EMMC(4),

	UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),

	UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),

	UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4),	/* =GIO0 */

	UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5),	/* =GIO1 */

	UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6),	/* =GIO1-1 */

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