Commit c2b8359d authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
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ath9k: Fix diversity combining for AR9285



When antenna diversity combining is enabled in the EEPROM,
the initial values for the MAIN/ALT config have to be
programmed correctly. This patch adds it for AR9285.

Since the diversity combining macros are common to all chip
families, remove the redundant AR9285 macros and move the
definitions to phy.h.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent a4df8f56
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+0 −4
Original line number Diff line number Diff line
@@ -317,10 +317,6 @@
#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S    29
#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB     0x40000000
#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S   30
#define AR_PHY_9285_ANT_DIV_LNA1            2
#define AR_PHY_9285_ANT_DIV_LNA2            1
#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2  3
#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
#define AR_PHY_9285_ANT_DIV_GAINTB_0        0
#define AR_PHY_9285_ANT_DIV_GAINTB_1        1

+2 −2
Original line number Diff line number Diff line
@@ -3673,9 +3673,9 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
				     AR_PHY_ANT_DIV_ALT_GAINTB |
				     AR_PHY_ANT_DIV_MAIN_GAINTB));
			/* by default use LNA1 for the main antenna */
			regval |= (AR_PHY_ANT_DIV_LNA1 <<
			regval |= (ATH_ANT_DIV_COMB_LNA1 <<
				   AR_PHY_ANT_DIV_MAIN_LNACONF_S);
			regval |= (AR_PHY_ANT_DIV_LNA2 <<
			regval |= (ATH_ANT_DIV_COMB_LNA2 <<
				   AR_PHY_ANT_DIV_ALT_LNACONF_S);
			REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
		}
+2 −2
Original line number Diff line number Diff line
@@ -1465,8 +1465,8 @@ static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
			AR_PHY_ANT_DIV_ALT_LNACONF |
			AR_PHY_ANT_DIV_MAIN_GAINTB |
			AR_PHY_ANT_DIV_ALT_GAINTB);
		regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
		regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
		regval |= (ATH_ANT_DIV_COMB_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
		regval |= (ATH_ANT_DIV_COMB_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
	}
}
+0 −5
Original line number Diff line number Diff line
@@ -296,11 +296,6 @@
#define AR_PHY_ANT_DIV_MAIN_GAINTB              0x40000000
#define AR_PHY_ANT_DIV_MAIN_GAINTB_S            30

#define AR_PHY_ANT_DIV_LNA1_MINUS_LNA2          0x0
#define AR_PHY_ANT_DIV_LNA2                     0x1
#define AR_PHY_ANT_DIV_LNA1                     0x2
#define AR_PHY_ANT_DIV_LNA1_PLUS_LNA2           0x3

#define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
#define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
#define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)
+0 −7
Original line number Diff line number Diff line
@@ -591,13 +591,6 @@ static inline void ath_fill_led_pin(struct ath_softc *sc)
#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2

enum ath9k_ant_div_comb_lna_conf {
	ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
	ATH_ANT_DIV_COMB_LNA2,
	ATH_ANT_DIV_COMB_LNA1,
	ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
};

struct ath_ant_comb {
	u16 count;
	u16 total_pkt_count;
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