Merge branch 'intel' (c2962897) · Commits · 戴 / test

drivers/net/ethernet/intel/igb/e1000_82575.c

+190 −62

Original line number	Original line	Diff line number	Diff line
	@@ -100,6 +100,7 @@ static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
	break;		break;
	case e1000_82580:		case e1000_82580:
	case e1000_i350:		case e1000_i350:
			case e1000_i354:
	case e1000_i210:		case e1000_i210:
	case e1000_i211:		case e1000_i211:
	reg = rd32(E1000_MDICNFG);		reg = rd32(E1000_MDICNFG);
	@@ -149,6 +150,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
	switch (hw->mac.type) {		switch (hw->mac.type) {
	case e1000_82580:		case e1000_82580:
	case e1000_i350:		case e1000_i350:
			case e1000_i354:
	phy->ops.read_reg = igb_read_phy_reg_82580;		phy->ops.read_reg = igb_read_phy_reg_82580;
	phy->ops.write_reg = igb_write_phy_reg_82580;		phy->ops.write_reg = igb_write_phy_reg_82580;
	break;		break;
	@@ -174,13 +176,14 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)

	/* Verify phy id and set remaining function pointers */		/* Verify phy id and set remaining function pointers */
	switch (phy->id) {		switch (phy->id) {
			case M88E1545_E_PHY_ID:
	case I347AT4_E_PHY_ID:		case I347AT4_E_PHY_ID:
	case M88E1112_E_PHY_ID:		case M88E1112_E_PHY_ID:
	case M88E1111_I_PHY_ID:		case M88E1111_I_PHY_ID:
	phy->type = e1000_phy_m88;		phy->type = e1000_phy_m88;
			phy->ops.check_polarity = igb_check_polarity_m88;
	phy->ops.get_phy_info = igb_get_phy_info_m88;		phy->ops.get_phy_info = igb_get_phy_info_m88;
	if (phy->id == I347AT4_E_PHY_ID \|\|		if (phy->id != M88E1111_I_PHY_ID)
	phy->id == M88E1112_E_PHY_ID)
	phy->ops.get_cable_length =		phy->ops.get_cable_length =
	igb_get_cable_length_m88_gen2;		igb_get_cable_length_m88_gen2;
	else		else
	@@ -227,7 +230,7 @@ out:
	* igb_init_nvm_params_82575 - Init NVM func ptrs.		* igb_init_nvm_params_82575 - Init NVM func ptrs.
	* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
	**/		**/
	s32 igb_init_nvm_params_82575(struct e1000_hw *hw)		static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
	{		{
	struct e1000_nvm_info *nvm = &hw->nvm;		struct e1000_nvm_info *nvm = &hw->nvm;
	u32 eecd = rd32(E1000_EECD);		u32 eecd = rd32(E1000_EECD);
	@@ -287,6 +290,7 @@ s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
	nvm->ops.read = igb_read_nvm_spi;		nvm->ops.read = igb_read_nvm_spi;
	nvm->ops.write = igb_write_nvm_spi;		nvm->ops.write = igb_write_nvm_spi;
	break;		break;
			case e1000_i354:
	case e1000_i350:		case e1000_i350:
	nvm->ops.validate = igb_validate_nvm_checksum_i350;		nvm->ops.validate = igb_validate_nvm_checksum_i350;
	nvm->ops.update = igb_update_nvm_checksum_i350;		nvm->ops.update = igb_update_nvm_checksum_i350;
	@@ -352,6 +356,7 @@ static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
	mac->rar_entry_count = E1000_RAR_ENTRIES_82580;		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
	break;		break;
	case e1000_i350:		case e1000_i350:
			case e1000_i354:
	mac->rar_entry_count = E1000_RAR_ENTRIES_I350;		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
	break;		break;
	default:		default:
	@@ -445,14 +450,18 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	case E1000_DEV_ID_I211_COPPER:		case E1000_DEV_ID_I211_COPPER:
	mac->type = e1000_i211;		mac->type = e1000_i211;
	break;		break;
			case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
			case E1000_DEV_ID_I354_SGMII:
			case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
			mac->type = e1000_i354;
			break;
	default:		default:
	return -E1000_ERR_MAC_INIT;		return -E1000_ERR_MAC_INIT;
	break;		break;
	}		}

	/* Set media type */		/* Set media type */
	/*		/* The 82575 uses bits 22:23 for link mode. The mode can be changed
	* The 82575 uses bits 22:23 for link mode. The mode can be changed
	* based on the EEPROM. We cannot rely upon device ID. There		* based on the EEPROM. We cannot rely upon device ID. There
	* is no distinguishable difference between fiber and internal		* is no distinguishable difference between fiber and internal
	* SerDes mode on the 82575. There can be an external PHY attached		* SerDes mode on the 82575. There can be an external PHY attached
	@@ -621,8 +630,7 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
	u32 ctrl_ext;		u32 ctrl_ext;
	u32 mdic;		u32 mdic;

	/*		/* For SGMII PHYs, we try the list of possible addresses until
	* For SGMII PHYs, we try the list of possible addresses until
	* we find one that works. For non-SGMII PHYs		* we find one that works. For non-SGMII PHYs
	* (e.g. integrated copper PHYs), an address of 1 should		* (e.g. integrated copper PHYs), an address of 1 should
	* work. The result of this function should mean phy->phy_addr		* work. The result of this function should mean phy->phy_addr
	@@ -644,6 +652,7 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
	break;		break;
	case e1000_82580:		case e1000_82580:
	case e1000_i350:		case e1000_i350:
			case e1000_i354:
	case e1000_i210:		case e1000_i210:
	case e1000_i211:		case e1000_i211:
	mdic = rd32(E1000_MDICNFG);		mdic = rd32(E1000_MDICNFG);
	@@ -665,8 +674,7 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
	wrfl();		wrfl();
	msleep(300);		msleep(300);

	/*		/* The address field in the I2CCMD register is 3 bits and 0 is invalid.
	* The address field in the I2CCMD register is 3 bits and 0 is invalid.
	* Therefore, we need to test 1-7		* Therefore, we need to test 1-7
	*/		*/
	for (phy->addr = 1; phy->addr < 8; phy->addr++) {		for (phy->addr = 1; phy->addr < 8; phy->addr++) {
	@@ -674,8 +682,7 @@ static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
	if (ret_val == 0) {		if (ret_val == 0) {
	hw_dbg("Vendor ID 0x%08X read at address %u\n",		hw_dbg("Vendor ID 0x%08X read at address %u\n",
	phy_id, phy->addr);		phy_id, phy->addr);
	/*		/* At the time of this writing, The M88 part is
	* At the time of this writing, The M88 part is
	* the only supported SGMII PHY product.		* the only supported SGMII PHY product.
	*/		*/
	if (phy_id == M88_VENDOR)		if (phy_id == M88_VENDOR)
	@@ -711,15 +718,13 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
	{		{
	s32 ret_val;		s32 ret_val;

	/*		/* This isn't a true "hard" reset, but is the only reset
	* This isn't a true "hard" reset, but is the only reset
	* available to us at this time.		* available to us at this time.
	*/		*/

	hw_dbg("Soft resetting SGMII attached PHY...\n");		hw_dbg("Soft resetting SGMII attached PHY...\n");

	/*		/* SFP documentation requires the following to configure the SPF module
	* SFP documentation requires the following to configure the SPF module
	* to work on SGMII. No further documentation is given.		* to work on SGMII. No further documentation is given.
	*/		*/
	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);		ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
	@@ -774,8 +779,7 @@ static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
	data &= ~IGP02E1000_PM_D0_LPLU;		data &= ~IGP02E1000_PM_D0_LPLU;
	ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
	data);		data);
	/*		/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
	* LPLU and SmartSpeed are mutually exclusive. LPLU is used
	* during Dx states where the power conservation is most		* during Dx states where the power conservation is most
	* important. During driver activity we should enable		* important. During driver activity we should enable
	* SmartSpeed, so performance is maintained.		* SmartSpeed, so performance is maintained.
	@@ -838,8 +842,7 @@ static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
	} else {		} else {
	data &= ~E1000_82580_PM_D0_LPLU;		data &= ~E1000_82580_PM_D0_LPLU;

	/*		/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
	* LPLU and SmartSpeed are mutually exclusive. LPLU is used
	* during Dx states where the power conservation is most		* during Dx states where the power conservation is most
	* important. During driver activity we should enable		* important. During driver activity we should enable
	* SmartSpeed, so performance is maintained.		* SmartSpeed, so performance is maintained.
	@@ -867,7 +870,7 @@ static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
	* During driver activity, SmartSpeed should be enabled so performance is		* During driver activity, SmartSpeed should be enabled so performance is
	* maintained.		* maintained.
	**/		**/
	s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)		static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
	{		{
	struct e1000_phy_info *phy = &hw->phy;		struct e1000_phy_info *phy = &hw->phy;
	s32 ret_val = 0;		s32 ret_val = 0;
	@@ -877,8 +880,7 @@ s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)

	if (!active) {		if (!active) {
	data &= ~E1000_82580_PM_D3_LPLU;		data &= ~E1000_82580_PM_D3_LPLU;
	/*		/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
	* LPLU and SmartSpeed are mutually exclusive. LPLU is used
	* during Dx states where the power conservation is most		* during Dx states where the power conservation is most
	* important. During driver activity we should enable		* important. During driver activity we should enable
	* SmartSpeed, so performance is maintained.		* SmartSpeed, so performance is maintained.
	@@ -964,8 +966,7 @@ static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
	if (!(swfw_sync & (fwmask \| swmask)))		if (!(swfw_sync & (fwmask \| swmask)))
	break;		break;

	/*		/* Firmware currently using resource (fwmask)
	* Firmware currently using resource (fwmask)
	* or other software thread using resource (swmask)		* or other software thread using resource (swmask)
	*/		*/
	igb_put_hw_semaphore(hw);		igb_put_hw_semaphore(hw);
	@@ -1065,8 +1066,7 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw)
	if (hw->phy.media_type != e1000_media_type_copper) {		if (hw->phy.media_type != e1000_media_type_copper) {
	ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,		ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
	&duplex);		&duplex);
	/*		/* Use this flag to determine if link needs to be checked or
	* Use this flag to determine if link needs to be checked or
	* not. If we have link clear the flag so that we do not		* not. If we have link clear the flag so that we do not
	* continue to check for link.		* continue to check for link.
	*/		*/
	@@ -1135,15 +1135,13 @@ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw hw, u16 speed,
	*speed = 0;		*speed = 0;
	*duplex = 0;		*duplex = 0;

	/*		/* Read the PCS Status register for link state. For non-copper mode,
	* Read the PCS Status register for link state. For non-copper mode,
	* the status register is not accurate. The PCS status register is		* the status register is not accurate. The PCS status register is
	* used instead.		* used instead.
	*/		*/
	pcs = rd32(E1000_PCS_LSTAT);		pcs = rd32(E1000_PCS_LSTAT);

	/*		/* The link up bit determines when link is up on autoneg. The sync ok
	* The link up bit determines when link is up on autoneg. The sync ok
	* gets set once both sides sync up and agree upon link. Stable link		* gets set once both sides sync up and agree upon link. Stable link
	* can be determined by checking for both link up and link sync ok		* can be determined by checking for both link up and link sync ok
	*/		*/
	@@ -1214,8 +1212,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)
	u32 ctrl, icr;		u32 ctrl, icr;
	s32 ret_val;		s32 ret_val;

	/*		/* Prevent the PCI-E bus from sticking if there is no TLP connection
	* Prevent the PCI-E bus from sticking if there is no TLP connection
	* on the last TLP read/write transaction when MAC is reset.		* on the last TLP read/write transaction when MAC is reset.
	*/		*/
	ret_val = igb_disable_pcie_master(hw);		ret_val = igb_disable_pcie_master(hw);
	@@ -1244,8 +1241,7 @@ static s32 igb_reset_hw_82575(struct e1000_hw *hw)

	ret_val = igb_get_auto_rd_done(hw);		ret_val = igb_get_auto_rd_done(hw);
	if (ret_val) {		if (ret_val) {
	/*		/* When auto config read does not complete, do not
	* When auto config read does not complete, do not
	* return with an error. This can happen in situations		* return with an error. This can happen in situations
	* where there is no eeprom and prevents getting link.		* where there is no eeprom and prevents getting link.
	*/		*/
	@@ -1287,7 +1283,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)

	/* Disabling VLAN filtering */		/* Disabling VLAN filtering */
	hw_dbg("Initializing the IEEE VLAN\n");		hw_dbg("Initializing the IEEE VLAN\n");
	if (hw->mac.type == e1000_i350)		if ((hw->mac.type == e1000_i350) \|\| (hw->mac.type == e1000_i354))
	igb_clear_vfta_i350(hw);		igb_clear_vfta_i350(hw);
	else		else
	igb_clear_vfta(hw);		igb_clear_vfta(hw);
	@@ -1308,8 +1304,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw)
	/* Setup link and flow control */		/* Setup link and flow control */
	ret_val = igb_setup_link(hw);		ret_val = igb_setup_link(hw);

	/*		/* Clear all of the statistics registers (clear on read). It is
	* Clear all of the statistics registers (clear on read). It is
	* important that we do this after we have tried to establish link		* important that we do this after we have tried to establish link
	* because the symbol error count will increment wildly if there		* because the symbol error count will increment wildly if there
	* is no link.		* is no link.
	@@ -1364,6 +1359,7 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
	switch (hw->phy.id) {		switch (hw->phy.id) {
	case I347AT4_E_PHY_ID:		case I347AT4_E_PHY_ID:
	case M88E1112_E_PHY_ID:		case M88E1112_E_PHY_ID:
			case M88E1545_E_PHY_ID:
	case I210_I_PHY_ID:		case I210_I_PHY_ID:
	ret_val = igb_copper_link_setup_m88_gen2(hw);		ret_val = igb_copper_link_setup_m88_gen2(hw);
	break;		break;
	@@ -1412,17 +1408,17 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
	return ret_val;		return ret_val;


	/*		/* On the 82575, SerDes loopback mode persists until it is
	* On the 82575, SerDes loopback mode persists until it is
	* explicitly turned off or a power cycle is performed. A read to		* explicitly turned off or a power cycle is performed. A read to
	* the register does not indicate its status. Therefore, we ensure		* the register does not indicate its status. Therefore, we ensure
	* loopback mode is disabled during initialization.		* loopback mode is disabled during initialization.
	*/		*/
	wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);		wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);

	/* power on the sfp cage if present */		/* power on the sfp cage if present and turn on I2C */
	ctrl_ext = rd32(E1000_CTRL_EXT);		ctrl_ext = rd32(E1000_CTRL_EXT);
	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;		ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
			ctrl_ext \|= E1000_CTRL_I2C_ENA;
	wr32(E1000_CTRL_EXT, ctrl_ext);		wr32(E1000_CTRL_EXT, ctrl_ext);

	ctrl_reg = rd32(E1000_CTRL);		ctrl_reg = rd32(E1000_CTRL);
	@@ -1466,8 +1462,7 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
	pcs_autoneg = false;		pcs_autoneg = false;
	}		}

	/*		/* non-SGMII modes only supports a speed of 1000/Full for the
	* non-SGMII modes only supports a speed of 1000/Full for the
	* link so it is best to just force the MAC and let the pcs		* link so it is best to just force the MAC and let the pcs
	* link either autoneg or be forced to 1000/Full		* link either autoneg or be forced to 1000/Full
	*/		*/
	@@ -1481,8 +1476,7 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)

	wr32(E1000_CTRL, ctrl_reg);		wr32(E1000_CTRL, ctrl_reg);

	/*		/* New SerDes mode allows for forcing speed or autonegotiating speed
	* New SerDes mode allows for forcing speed or autonegotiating speed
	* at 1gb. Autoneg should be default set by most drivers. This is the		* at 1gb. Autoneg should be default set by most drivers. This is the
	* mode that will be compatible with older link partners and switches.		* mode that will be compatible with older link partners and switches.
	* However, both are supported by the hardware and some drivers/tools.		* However, both are supported by the hardware and some drivers/tools.
	@@ -1592,8 +1586,7 @@ static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
	{		{
	s32 ret_val = 0;		s32 ret_val = 0;

	/*		/* If there's an alternate MAC address place it in RAR0
	* If there's an alternate MAC address place it in RAR0
	* so that it will override the Si installed default perm		* so that it will override the Si installed default perm
	* address.		* address.
	*/		*/
	@@ -1777,8 +1770,7 @@ static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
	if (gcr & E1000_GCR_CMPL_TMOUT_MASK)		if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
	goto out;		goto out;

	/*		/* if capabilities version is type 1 we can write the
	* if capababilities version is type 1 we can write the
	* timeout of 10ms to 200ms through the GCR register		* timeout of 10ms to 200ms through the GCR register
	*/		*/
	if (!(gcr & E1000_GCR_CAP_VER2)) {		if (!(gcr & E1000_GCR_CAP_VER2)) {
	@@ -1786,8 +1778,7 @@ static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
	goto out;		goto out;
	}		}

	/*		/* for version 2 capabilities we need to write the config space
	* for version 2 capabilities we need to write the config space
	* directly in order to set the completion timeout value for		* directly in order to set the completion timeout value for
	* 16ms to 55ms		* 16ms to 55ms
	*/		*/
	@@ -1825,6 +1816,7 @@ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
	reg_offset = E1000_DTXSWC;		reg_offset = E1000_DTXSWC;
	break;		break;
	case e1000_i350:		case e1000_i350:
			case e1000_i354:
	reg_offset = E1000_TXSWC;		reg_offset = E1000_TXSWC;
	break;		break;
	default:		default:
	@@ -1866,6 +1858,7 @@ void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
	dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;		dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
	wr32(E1000_DTXSWC, dtxswc);		wr32(E1000_DTXSWC, dtxswc);
	break;		break;
			case e1000_i354:
	case e1000_i350:		case e1000_i350:
	dtxswc = rd32(E1000_TXSWC);		dtxswc = rd32(E1000_TXSWC);
	if (enable)		if (enable)
	@@ -1879,7 +1872,6 @@ void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
	break;		break;
	}		}


	}		}

	/**		/**
	@@ -1914,7 +1906,6 @@ static s32 igb_read_phy_reg_82580(struct e1000_hw hw, u32 offset, u16 data)
	{		{
	s32 ret_val;		s32 ret_val;


	ret_val = hw->phy.ops.acquire(hw);		ret_val = hw->phy.ops.acquire(hw);
	if (ret_val)		if (ret_val)
	goto out;		goto out;
	@@ -2016,8 +2007,7 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)
	/* Get current control state. */		/* Get current control state. */
	ctrl = rd32(E1000_CTRL);		ctrl = rd32(E1000_CTRL);

	/*		/* Prevent the PCI-E bus from sticking if there is no TLP connection
	* Prevent the PCI-E bus from sticking if there is no TLP connection
	* on the last TLP read/write transaction when MAC is reset.		* on the last TLP read/write transaction when MAC is reset.
	*/		*/
	ret_val = igb_disable_pcie_master(hw);		ret_val = igb_disable_pcie_master(hw);
	@@ -2052,8 +2042,7 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)

	ret_val = igb_get_auto_rd_done(hw);		ret_val = igb_get_auto_rd_done(hw);
	if (ret_val) {		if (ret_val) {
	/*		/* When auto config read does not complete, do not
	* When auto config read does not complete, do not
	* return with an error. This can happen in situations		* return with an error. This can happen in situations
	* where there is no eeprom and prevents getting link.		* where there is no eeprom and prevents getting link.
	*/		*/
	@@ -2197,7 +2186,8 @@ static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)

	if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {		if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
	/* if checksums compatibility bit is set validate checksums		/* if checksums compatibility bit is set validate checksums
	* for all 4 ports. */		* for all 4 ports.
			*/
	eeprom_regions_count = 4;		eeprom_regions_count = 4;
	}		}

	@@ -2308,6 +2298,41 @@ out:
	return ret_val;		return ret_val;
	}		}

			/**
			* __igb_access_emi_reg - Read/write EMI register
			* @hw: pointer to the HW structure
			* @addr: EMI address to program
			* @data: pointer to value to read/write from/to the EMI address
			* @read: boolean flag to indicate read or write
			**/
			static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
			u16 *data, bool read)
			{
			s32 ret_val = E1000_SUCCESS;

			ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
			if (ret_val)
			return ret_val;

			if (read)
			ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
			else
			ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);

			return ret_val;
			}

			/**
			* igb_read_emi_reg - Read Extended Management Interface register
			* @hw: pointer to the HW structure
			* @addr: EMI address to program
			* @data: value to be read from the EMI address
			**/
			s32 igb_read_emi_reg(struct e1000_hw hw, u16 addr, u16 data)
			{
			return __igb_access_emi_reg(hw, addr, data, true);
			}

	/**		/**
	* igb_set_eee_i350 - Enable/disable EEE support		* igb_set_eee_i350 - Enable/disable EEE support
	* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
	@@ -2338,7 +2363,6 @@ s32 igb_set_eee_i350(struct e1000_hw *hw)
	if (eee_su & E1000_EEE_SU_LPI_CLK_STP)		if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
	hw_dbg("LPI Clock Stop Bit should not be set!\n");		hw_dbg("LPI Clock Stop Bit should not be set!\n");


	} else {		} else {
	ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN \|		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN \|
	E1000_IPCNFG_EEE_100M_AN);		E1000_IPCNFG_EEE_100M_AN);
	@@ -2355,6 +2379,108 @@ out:
	return ret_val;		return ret_val;
	}		}

			/**
			* igb_set_eee_i354 - Enable/disable EEE support
			* @hw: pointer to the HW structure
			*
			* Enable/disable EEE legacy mode based on setting in dev_spec structure.
			*
			**/
			s32 igb_set_eee_i354(struct e1000_hw *hw)
			{
			struct e1000_phy_info *phy = &hw->phy;
			s32 ret_val = 0;
			u16 phy_data;

			if ((hw->phy.media_type != e1000_media_type_copper) \|\|
			(phy->id != M88E1545_E_PHY_ID))
			goto out;

			if (!hw->dev_spec._82575.eee_disable) {
			/* Switch to PHY page 18. */
			ret_val = phy->ops.write_reg(hw, E1000_M88E1545_PAGE_ADDR, 18);
			if (ret_val)
			goto out;

			ret_val = phy->ops.read_reg(hw, E1000_M88E1545_EEE_CTRL_1,
			&phy_data);
			if (ret_val)
			goto out;

			phy_data \|= E1000_M88E1545_EEE_CTRL_1_MS;
			ret_val = phy->ops.write_reg(hw, E1000_M88E1545_EEE_CTRL_1,
			phy_data);
			if (ret_val)
			goto out;

			/* Return the PHY to page 0. */
			ret_val = phy->ops.write_reg(hw, E1000_M88E1545_PAGE_ADDR, 0);
			if (ret_val)
			goto out;

			/* Turn on EEE advertisement. */
			ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
			E1000_EEE_ADV_DEV_I354,
			&phy_data);
			if (ret_val)
			goto out;

			phy_data \|= E1000_EEE_ADV_100_SUPPORTED \|
			E1000_EEE_ADV_1000_SUPPORTED;
			ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
			E1000_EEE_ADV_DEV_I354,
			phy_data);
			} else {
			/* Turn off EEE advertisement. */
			ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
			E1000_EEE_ADV_DEV_I354,
			&phy_data);
			if (ret_val)
			goto out;

			phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED \|
			E1000_EEE_ADV_1000_SUPPORTED);
			ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
			E1000_EEE_ADV_DEV_I354,
			phy_data);
			}

			out:
			return ret_val;
			}

			/**
			* igb_get_eee_status_i354 - Get EEE status
			* @hw: pointer to the HW structure
			* @status: EEE status
			*
			* Get EEE status by guessing based on whether Tx or Rx LPI indications have
			* been received.
			**/
			s32 igb_get_eee_status_i354(struct e1000_hw hw, bool status)
			{
			struct e1000_phy_info *phy = &hw->phy;
			s32 ret_val = 0;
			u16 phy_data;

			/* Check if EEE is supported on this device. */
			if ((hw->phy.media_type != e1000_media_type_copper) \|\|
			(phy->id != M88E1545_E_PHY_ID))
			goto out;

			ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
			E1000_PCS_STATUS_DEV_I354,
			&phy_data);
			if (ret_val)
			goto out;

			*status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD \|
			E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;

			out:
			return ret_val;
			}

	static const u8 e1000_emc_temp_data[4] = {		static const u8 e1000_emc_temp_data[4] = {
	E1000_EMC_INTERNAL_DATA,		E1000_EMC_INTERNAL_DATA,
	E1000_EMC_DIODE1_DATA,		E1000_EMC_DIODE1_DATA,
	@@ -2368,11 +2494,12 @@ static const u8 e1000_emc_therm_limit[4] = {
	E1000_EMC_DIODE3_THERM_LIMIT		E1000_EMC_DIODE3_THERM_LIMIT
	};		};

	/* igb_get_thermal_sensor_data_generic - Gathers thermal sensor data		/**
			* igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
	* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
	*		*
	* Updates the temperatures in mac.thermal_sensor_data		* Updates the temperatures in mac.thermal_sensor_data
	*/		**/
	s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)		s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
	{		{
	s32 status = E1000_SUCCESS;		s32 status = E1000_SUCCESS;
	@@ -2420,12 +2547,13 @@ s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
	return status;		return status;
	}		}

	/* igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds		/**
			* igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
	* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
	*		*
	* Sets the thermal sensor thresholds according to the NVM map		* Sets the thermal sensor thresholds according to the NVM map
	* and save off the threshold and location values into mac.thermal_sensor_data		* and save off the threshold and location values into mac.thermal_sensor_data
	*/		**/
	s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)		s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
	{		{
	s32 status = E1000_SUCCESS;		s32 status = E1000_SUCCESS;

drivers/net/ethernet/intel/igb/e1000_82575.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -263,7 +263,9 @@ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
	void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);		void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
	void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);		void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
	u16 igb_rxpbs_adjust_82580(u32 data);		u16 igb_rxpbs_adjust_82580(u32 data);
			s32 igb_read_emi_reg(struct e1000_hw , u16 addr, u16 data);
	s32 igb_set_eee_i350(struct e1000_hw *);		s32 igb_set_eee_i350(struct e1000_hw *);
			s32 igb_set_eee_i354(struct e1000_hw *);
	s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *);		s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *);
	s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw);		s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw);

drivers/net/ethernet/intel/igb/e1000_defines.h

+30 −20

Original line number	Original line	Diff line number	Diff line
	@@ -138,8 +138,7 @@
	#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */		#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
	#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */		#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */

	/*		/* Use byte values for the following shift parameters
	* Use byte values for the following shift parameters
	* Usage:		* Usage:
	* psrctl \|= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &		* psrctl \|= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
	* E1000_PSRCTL_BSIZE0_MASK) \|		* E1000_PSRCTL_BSIZE0_MASK) \|
	@@ -237,11 +236,14 @@
	#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000		#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
	/* BMC external code execution disabled */		/* BMC external code execution disabled */

			#define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
			#define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
	/* Constants used to intrepret the masked PCI-X bus speed. */		/* Constants used to intrepret the masked PCI-X bus speed. */

	#define SPEED_10 10		#define SPEED_10 10
	#define SPEED_100 100		#define SPEED_100 100
	#define SPEED_1000 1000		#define SPEED_1000 1000
			#define SPEED_2500 2500
	#define HALF_DUPLEX 1		#define HALF_DUPLEX 1
	#define FULL_DUPLEX 2		#define FULL_DUPLEX 2

	@@ -382,8 +384,7 @@
	#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */		#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
	/* TCP Timer */		/* TCP Timer */

	/*		/* This defines the bits that are set in the Interrupt Mask
	* This defines the bits that are set in the Interrupt Mask
	* Set/Read Register. Each bit is documented below:		* Set/Read Register. Each bit is documented below:
	* o RXT0 = Receiver Timer Interrupt (ring 0)		* o RXT0 = Receiver Timer Interrupt (ring 0)
	* o TXDW = Transmit Descriptor Written Back		* o TXDW = Transmit Descriptor Written Back
	@@ -440,8 +441,7 @@
	#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */		#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */

	/* Receive Address */		/* Receive Address */
	/*		/* Number of high/low register pairs in the RAR. The RAR (Receive Address
	* Number of high/low register pairs in the RAR. The RAR (Receive Address
	* Registers) holds the directed and multicast addresses that we monitor.		* Registers) holds the directed and multicast addresses that we monitor.
	* Technically, we have 16 spots. However, we reserve one of these spots		* Technically, we have 16 spots. However, we reserve one of these spots
	* (RAR[15]) for our directed address used by controllers with		* (RAR[15]) for our directed address used by controllers with
	@@ -760,8 +760,7 @@
	#define MAX_PHY_MULTI_PAGE_REG 0xF		#define MAX_PHY_MULTI_PAGE_REG 0xF

	/* Bit definitions for valid PHY IDs. */		/* Bit definitions for valid PHY IDs. */
	/*		/* I = Integrated
	* I = Integrated
	* E = External		* E = External
	*/		*/
	#define M88E1111_I_PHY_ID 0x01410CC0		#define M88E1111_I_PHY_ID 0x01410CC0
	@@ -772,6 +771,7 @@
	#define I350_I_PHY_ID 0x015403B0		#define I350_I_PHY_ID 0x015403B0
	#define M88_VENDOR 0x0141		#define M88_VENDOR 0x0141
	#define I210_I_PHY_ID 0x01410C00		#define I210_I_PHY_ID 0x01410C00
			#define M88E1545_E_PHY_ID 0x01410EA0

	/* M88E1000 Specific Registers */		/* M88E1000 Specific Registers */
	#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */		#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
	@@ -791,8 +791,7 @@
	#define M88E1000_PSCR_AUTO_X_1000T 0x0040		#define M88E1000_PSCR_AUTO_X_1000T 0x0040
	/* Auto crossover enabled all speeds */		/* Auto crossover enabled all speeds */
	#define M88E1000_PSCR_AUTO_X_MODE 0x0060		#define M88E1000_PSCR_AUTO_X_MODE 0x0060
	/*		/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
	* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
	* 0=Normal 10BASE-T Rx Threshold		* 0=Normal 10BASE-T Rx Threshold
	*/		*/
	/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */		/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
	@@ -802,8 +801,7 @@
	#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */		#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
	#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */		#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
	#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */		#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
	/*		/* 0 = <50M
	* 0 = <50M
	* 1 = 50-80M		* 1 = 50-80M
	* 2 = 80-110M		* 2 = 80-110M
	* 3 = 110-140M		* 3 = 110-140M
	@@ -816,20 +814,17 @@
	#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7		#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7

	/* M88E1000 Extended PHY Specific Control Register */		/* M88E1000 Extended PHY Specific Control Register */
	/*		/* 1 = Lost lock detect enabled.
	* 1 = Lost lock detect enabled.
	* Will assert lost lock and bring		* Will assert lost lock and bring
	* link down if idle not seen		* link down if idle not seen
	* within 1ms in 1000BASE-T		* within 1ms in 1000BASE-T
	*/		*/
	/*		/* Number of times we will attempt to autonegotiate before downshifting if we
	* Number of times we will attempt to autonegotiate before downshifting if we
	* are the master		* are the master
	*/		*/
	#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00		#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
	#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000		#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
	/*		/* Number of times we will attempt to autonegotiate before downshifting if we
	* Number of times we will attempt to autonegotiate before downshifting if we
	* are the slave		* are the slave
	*/		*/
	#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300		#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
	@@ -844,8 +839,7 @@

	/* i347-AT4 Extended PHY Specific Control Register */		/* i347-AT4 Extended PHY Specific Control Register */

	/*		/* Number of times we will attempt to autonegotiate before downshifting if we
	* Number of times we will attempt to autonegotiate before downshifting if we
	* are the master		* are the master
	*/		*/
	#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800		#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
	@@ -895,6 +889,22 @@
	#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */		#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */
	#define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */		#define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */
	#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */		#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
			#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
			#define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
			#define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
			#define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
			#define E1000_M88E1545_PAGE_ADDR 0x16 /* Page Offset Register */
			#define E1000_M88E1545_EEE_CTRL_1 0x0
			#define E1000_M88E1545_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
			#define E1000_EEE_ADV_DEV_I354 7
			#define E1000_EEE_ADV_ADDR_I354 60
			#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
			#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
			#define E1000_PCS_STATUS_DEV_I354 3
			#define E1000_PCS_STATUS_ADDR_I354 1
			#define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */
			#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
			#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800

	/* SerDes Control */		/* SerDes Control */
	#define E1000_GEN_CTL_READY 0x80000000		#define E1000_GEN_CTL_READY 0x80000000

drivers/net/ethernet/intel/igb/e1000_hw.h

+31 −26

Original line number	Original line	Diff line number	Diff line
	@@ -70,6 +70,9 @@ struct e1000_hw;
	#define E1000_DEV_ID_I210_SERDES 0x1537		#define E1000_DEV_ID_I210_SERDES 0x1537
	#define E1000_DEV_ID_I210_SGMII 0x1538		#define E1000_DEV_ID_I210_SGMII 0x1538
	#define E1000_DEV_ID_I211_COPPER 0x1539		#define E1000_DEV_ID_I211_COPPER 0x1539
			#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
			#define E1000_DEV_ID_I354_SGMII 0x1F41
			#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45

	#define E1000_REVISION_2 2		#define E1000_REVISION_2 2
	#define E1000_REVISION_4 4		#define E1000_REVISION_4 4
	@@ -90,6 +93,7 @@ enum e1000_mac_type {
	e1000_82576,		e1000_82576,
	e1000_82580,		e1000_82580,
	e1000_i350,		e1000_i350,
			e1000_i354,
	e1000_i210,		e1000_i210,
	e1000_i211,		e1000_i211,
	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */		e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	@@ -98,7 +102,8 @@ enum e1000_mac_type {
	enum e1000_media_type {		enum e1000_media_type {
	e1000_media_type_unknown = 0,		e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,		e1000_media_type_copper = 1,
	e1000_media_type_internal_serdes = 2,		e1000_media_type_fiber = 2,
			e1000_media_type_internal_serdes = 3,
	e1000_num_media_types		e1000_num_media_types
	};		};

drivers/net/ethernet/intel/igb/e1000_i210.c

+76 −17

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