x86: hpet: stop HPET_COUNTER when programming periodic mode (c23e253e) · Commits · 戴 / test

Impact: fix system hang on some systems operating with HZ_1000 On a system that stalled with HZ_1000, the first value written to T0_CMP (when the main counter was not stopped) did not trigger an interrupt. Instead after the main counter wrapped around (after several minutes) an interrupt was triggered and afterwards the periodic interrupt took effect. This can be fixed by implementing HPET spec recommendation for programming the periodic mode (i.e. stopping the main counter). Signed-off-by:

Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Mark Hounschell <markh@compro.net> Cc: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by:

Ingo Molnar <mingo@elte.hu>

arch/x86/kernel/hpet.c

+3 −10

Original line number	Diff line number	Diff line
		@@ -309,29 +309,22 @@ static int hpet_setup_msi_irq(unsigned int irq);
		static void hpet_set_mode(enum clock_event_mode mode,
		struct clock_event_device *evt, int timer)
		{
		unsigned long cfg, cmp, now;
		unsigned long cfg;
		uint64_t delta;

		switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
		hpet_stop_counter();
		delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
		delta >>= evt->shift;
		now = hpet_readl(HPET_COUNTER);
		cmp = now + (unsigned long) delta;
		cfg = hpet_readl(HPET_Tn_CFG(timer));
		/* Make sure we use edge triggered interrupts */
		cfg &= ~HPET_TN_LEVEL;
		cfg \|= HPET_TN_ENABLE \| HPET_TN_PERIODIC \|
		HPET_TN_SETVAL \| HPET_TN_32BIT;
		hpet_writel(cfg, HPET_Tn_CFG(timer));
		/*
		* The first write after writing TN_SETVAL to the
		* config register sets the counter value, the second
		* write sets the period.
		*/
		hpet_writel(cmp, HPET_Tn_CMP(timer));
		udelay(1);
		hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
		hpet_start_counter();
		hpet_print_config();
		break;

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