Commit c2377a42 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Move definition of SMP processor id register to header file 



The definition of the CP0 register used to save the smp processor
id is repicated in many files, move them all to thread_info.h.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5708/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1a9db0a9

arch/mips/include/asm/mmu_context.h

+5 −11
Original line number Diff line number Diff line
@@ -35,10 +35,11 @@ do { \ 
#define TLBMISS_HANDLER_SETUP()						\

	do {								\

		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\

		write_c0_xcontext((unsigned long) smp_processor_id() << 51); \

		write_c0_xcontext((unsigned long) smp_processor_id() <<	\

						SMP_CPUID_REGSHIFT);	\

	} while (0)



#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/

#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/



/*

 * For the fast tlb miss handlers, we keep a per cpu array of pointers
@@ -50,18 +51,11 @@ extern unsigned long pgd_current[]; 
#define TLBMISS_HANDLER_SETUP_PGD(pgd) \

	pgd_current[smp_processor_id()] = (unsigned long)(pgd)



#ifdef CONFIG_32BIT

#define TLBMISS_HANDLER_SETUP()						\

	write_c0_context((unsigned long) smp_processor_id() << 25);	\

	write_c0_context((unsigned long) smp_processor_id() <<		\

						SMP_CPUID_REGSHIFT);	\

	back_to_back_c0_hazard();					\

	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)

#endif

#ifdef CONFIG_64BIT

#define TLBMISS_HANDLER_SETUP()						\

	write_c0_context((unsigned long) smp_processor_id() << 26);	\

	back_to_back_c0_hazard();					\

	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)

#endif

#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/

#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

arch/mips/include/asm/stackframe.h

+6 −18
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <asm/asmmacro.h>

#include <asm/mipsregs.h>

#include <asm/asm-offsets.h>

#include <asm/thread_info.h>



/*

 * For SMTC kernel, global IE should be left set, and interrupts
@@ -93,21 +94,8 @@ 
		.endm



#ifdef CONFIG_SMP

#ifdef CONFIG_MIPS_MT_SMTC

#define PTEBASE_SHIFT	19	/* TCBIND */

#define CPU_ID_REG CP0_TCBIND

#define CPU_ID_MFC0 mfc0

#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)

#define PTEBASE_SHIFT	48	/* XCONTEXT */

#define CPU_ID_REG CP0_XCONTEXT

#define CPU_ID_MFC0 MFC0

#else

#define PTEBASE_SHIFT	23	/* CONTEXT */

#define CPU_ID_REG CP0_CONTEXT

#define CPU_ID_MFC0 MFC0

#endif

		.macro	get_saved_sp	/* SMP variation */

		CPU_ID_MFC0	k0, CPU_ID_REG

		ASM_CPUID_MFC0	k0, ASM_SMP_CPUID_REG

#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)

		lui	k1, %hi(kernelsp)

#else
@@ -117,17 +105,17 @@ 
		daddiu	k1, %hi(kernelsp)

		dsll	k1, 16

#endif

		LONG_SRL	k0, PTEBASE_SHIFT

		LONG_SRL	k0, SMP_CPUID_PTRSHIFT

		LONG_ADDU	k1, k0

		LONG_L	k1, %lo(kernelsp)(k1)

		.endm



		.macro	set_saved_sp stackp temp temp2

		CPU_ID_MFC0	\temp, CPU_ID_REG

		LONG_SRL	\temp, PTEBASE_SHIFT

		ASM_CPUID_MFC0	\temp, ASM_SMP_CPUID_REG

		LONG_SRL	\temp, SMP_CPUID_PTRSHIFT

		LONG_S	\stackp, kernelsp(\temp)

		.endm

#else

#else /* !CONFIG_SMP */

		.macro	get_saved_sp	/* Uniprocessor variation */

#ifdef CONFIG_CPU_JUMP_WORKAROUNDS

		/*

arch/mips/include/asm/thread_info.h

+32 −1
Original line number Diff line number Diff line
@@ -147,6 +147,37 @@ static inline struct thread_info *current_thread_info(void) 
#define _TIF_ALLWORK_MASK	(_TIF_NOHZ | _TIF_WORK_MASK |		\

				 _TIF_WORK_SYSCALL_EXIT)



#endif /* __KERNEL__ */

/*

 * We stash processor id into a COP0 register to retrieve it fast

 * at kernel exception entry.

 */

#if defined(CONFIG_MIPS_MT_SMTC)

#define SMP_CPUID_REG		2, 2	/* TCBIND */

#define ASM_SMP_CPUID_REG	$2, 2

#define SMP_CPUID_PTRSHIFT	19

#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)

#define SMP_CPUID_REG		20, 0	/* XCONTEXT */

#define ASM_SMP_CPUID_REG	$20

#define SMP_CPUID_PTRSHIFT	48

#else

#define SMP_CPUID_REG		4, 0	/* CONTEXT */

#define ASM_SMP_CPUID_REG	$4

#define SMP_CPUID_PTRSHIFT	23

#endif



#ifdef CONFIG_64BIT

#define SMP_CPUID_REGSHIFT	(SMP_CPUID_PTRSHIFT + 3)

#else

#define SMP_CPUID_REGSHIFT	(SMP_CPUID_PTRSHIFT + 2)

#endif



#ifdef CONFIG_MIPS_MT_SMTC

#define ASM_CPUID_MFC0		mfc0

#define UASM_i_CPUID_MFC0	uasm_i_mfc0

#else

#define ASM_CPUID_MFC0		MFC0

#define UASM_i_CPUID_MFC0	UASM_i_MFC0

#endif



#endif /* __KERNEL__ */

#endif /* _ASM_THREAD_INFO_H */

arch/mips/mm/tlbex.c

+6 −50
Original line number Diff line number Diff line
@@ -340,10 +340,6 @@ static struct work_registers build_get_work_registers(u32 **p) 
{

	struct work_registers r;



	int smp_processor_id_reg;

	int smp_processor_id_sel;

	int smp_processor_id_shift;



	if (scratch_reg >= 0) {

		/* Save in CPU local C0_KScratch? */

		UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
@@ -354,25 +350,9 @@ static struct work_registers build_get_work_registers(u32 **p) 
	}



	if (num_possible_cpus() > 1) {

#ifdef CONFIG_MIPS_PGD_C0_CONTEXT

		smp_processor_id_shift = 51;

		smp_processor_id_reg = 20; /* XContext */

		smp_processor_id_sel = 0;

#else

# ifdef CONFIG_32BIT

		smp_processor_id_shift = 25;

		smp_processor_id_reg = 4; /* Context */

		smp_processor_id_sel = 0;

# endif

# ifdef CONFIG_64BIT

		smp_processor_id_shift = 26;

		smp_processor_id_reg = 4; /* Context */

		smp_processor_id_sel = 0;

# endif

#endif

		/* Get smp_processor_id */

		UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel);

		UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift);

		UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);

		UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);



		/* handler_reg_save index in K0 */

		UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
@@ -837,20 +817,8 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 
		uasm_i_drotr(p, ptr, ptr, 11);

	}

#elif defined(CONFIG_SMP)

# ifdef	 CONFIG_MIPS_MT_SMTC

	/*

	 * SMTC uses TCBind value as "CPU" index

	 */

	uasm_i_mfc0(p, ptr, C0_TCBIND);

	uasm_i_dsrl_safe(p, ptr, ptr, 19);

# else

	/*

	 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3

	 * stored in CONTEXT.

	 */

	uasm_i_dmfc0(p, ptr, C0_CONTEXT);

	uasm_i_dsrl_safe(p, ptr, ptr, 23);

# endif

	UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);

	uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);

	UASM_i_LA_mostly(p, tmp, pgdc);

	uasm_i_daddu(p, ptr, ptr, tmp);

	uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -957,21 +925,9 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 


	/* 32 bit SMP has smp_processor_id() stored in CONTEXT. */

#ifdef CONFIG_SMP

#ifdef	CONFIG_MIPS_MT_SMTC

	/*

	 * SMTC uses TCBind value as "CPU" index

	 */

	uasm_i_mfc0(p, ptr, C0_TCBIND);

	uasm_i_mfc0(p, ptr, SMP_CPUID_REG);

	UASM_i_LA_mostly(p, tmp, pgdc);

	uasm_i_srl(p, ptr, ptr, 19);

#else

	/*

	 * smp_processor_id() << 2 is stored in CONTEXT.

	 */

	uasm_i_mfc0(p, ptr, C0_CONTEXT);

	UASM_i_LA_mostly(p, tmp, pgdc);

	uasm_i_srl(p, ptr, ptr, 23);

#endif

	uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);

	uasm_i_addu(p, ptr, tmp, ptr);

#else

	UASM_i_LA_mostly(p, ptr, pgdc);

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