drm/i915/ehl: Ungate DDIC and DDID (c2052d6e) · Commits · 戴 / test

Specification states that DDI_CLK_SEL needs to be mapped to MG clock even if MG do not exist on EHL, this will ungate those DDIs. BSpec: 20845 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Signed-off-by:

José Roberto de Souza <jose.souza@intel.com> Reviewed-by:

Matt Roper <matthew.d.roper@intel.com> Tested-by:

Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730175121.16413-1-jose.souza@intel.com

drivers/gpu/drm/i915/display/intel_ddi.c

+8 −1

Original line number	Diff line number	Diff line
		@@ -2921,6 +2921,12 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
		if (!intel_phy_is_combo(dev_priv, phy))
		I915_WRITE(DDI_CLK_SEL(port),
		icl_pll_to_ddi_clk_sel(encoder, crtc_state));
		else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
		/*
		* MG does not exist but the programming is required
		* to ungate DDIC and DDID
		*/
		I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
		} else if (IS_CANNONLAKE(dev_priv)) {
		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
		val = I915_READ(DPCLKA_CFGCR0);
		@@ -2961,7 +2967,8 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
		enum phy phy = intel_port_to_phy(dev_priv, port);

		if (INTEL_GEN(dev_priv) >= 11) {
		if (!intel_phy_is_combo(dev_priv, phy))
		if (!intel_phy_is_combo(dev_priv, phy) \|\|
		(IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
		I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
		} else if (IS_CANNONLAKE(dev_priv)) {
		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) \|

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