Commit c1ff8431 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Peter Anvin:
 "Quite a varied little collection of fixes.  Most of them are
  relatively small or isolated; the biggest one is Mel Gorman's fixes
  for TLB range flushing.

  A couple of AMD-related fixes (including not crashing when given an
  invalid microcode image) and fix a crash when compiled with gcov"

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, microcode, AMD: Unify valid container checks
  x86, hweight: Fix BUG when booting with CONFIG_GCOV_PROFILE_ALL=y
  x86/efi: Allow mapping BGRT on x86-32
  x86: Fix the initialization of physnode_map
  x86, cpu hotplug: Fix stack frame warning in check_irq_vectors_for_cpu_disable()
  x86/intel/mid: Fix X86_INTEL_MID dependencies
  arch/x86/mm/srat: Skip NUMA_NO_NODE while parsing SLIT
  mm, x86: Revisit tlb_flushall_shift tuning for page flushes except on IvyBridge
  x86: mm: change tlb_flushall_shift for IvyBridge
  x86/mm: Eliminate redundant page table walk during TLB range flushing
  x86/mm: Clean up inconsistencies when flushing TLB ranges
  mm, x86: Account for TLB flushes only when debugging
  x86/AMD/NB: Fix amd_set_subcaches() parameter type
  x86/quirks: Add workaround for AMD F16h Erratum792
  x86, doc, kconfig: Fix dud URL for Microcode data
parents ec2e6cb2 a3b072cd

arch/x86/Kconfig

+4 −3
Original line number Diff line number Diff line
@@ -444,6 +444,7 @@ config X86_INTEL_MID 
	bool "Intel MID platform support"

	depends on X86_32

	depends on X86_EXTENDED_PLATFORM

	depends on X86_PLATFORM_DEVICES

	depends on PCI

	depends on PCI_GOANY

	depends on X86_IO_APIC
@@ -1051,9 +1052,9 @@ config MICROCODE_INTEL 
	  This options enables microcode patch loading support for Intel

	  processors.



	  For latest news and information on obtaining all the required

	  Intel ingredients for this driver, check:

	  <http://www.urbanmyth.org/microcode/>.

	  For the current Intel microcode data package go to

	  <https://downloadcenter.intel.com> and search for

	  'Linux Processor Microcode Data File'.



config MICROCODE_AMD

	bool "AMD microcode loading support"

arch/x86/include/asm/amd_nb.h

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ extern int amd_cache_northbridges(void); 
extern void amd_flush_garts(void);

extern int amd_numa_init(void);

extern int amd_get_subcaches(int);

extern int amd_set_subcaches(int, int);

extern int amd_set_subcaches(int, unsigned long);



struct amd_l3_cache {

	unsigned indices;

arch/x86/include/asm/tlbflush.h

+3 −3
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static inline void __flush_tlb_all(void) 


static inline void __flush_tlb_one(unsigned long addr)

{

	count_vm_event(NR_TLB_LOCAL_FLUSH_ONE);

	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);

	__flush_tlb_single(addr);

}
@@ -93,13 +93,13 @@ static inline void __flush_tlb_one(unsigned long addr) 
 */

static inline void __flush_tlb_up(void)

{

	count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);

	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);

	__flush_tlb();

}



static inline void flush_tlb_all(void)

{

	count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);

	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);

	__flush_tlb_all();

}

arch/x86/kernel/amd_nb.c

+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ int amd_get_subcaches(int cpu) 
	return (mask >> (4 * cuid)) & 0xf;

}



int amd_set_subcaches(int cpu, int mask)

int amd_set_subcaches(int cpu, unsigned long mask)

{

	static unsigned int reset, ban;

	struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));

arch/x86/kernel/cpu/amd.c

+1 −4
Original line number Diff line number Diff line
@@ -767,10 +767,7 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 


static void cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)

{

	tlb_flushall_shift = 5;



	if (c->x86 <= 0x11)

		tlb_flushall_shift = 4;

	tlb_flushall_shift = 6;

}



static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)

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