Commit c1ef3436 authored by Douglas Anderson's avatar Douglas Anderson Committed by Stephen Boyd
Browse files

clk: qcom: Get rid of the test clock for dispcc-sc7180 



The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Link: https://lkml.kernel.org/r/20200203103049.v4.5.I28ac8f801456f1b950f7da10ed0f74a1344d4a35@changeid


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 0a97e8a5

drivers/clk/qcom/dispcc-sc7180.c

+10 −22
Original line number Diff line number Diff line
@@ -76,38 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { 


static const struct parent_map disp_cc_parent_map_0[] = {

	{ P_BI_TCXO, 0 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data disp_cc_parent_data_0[] = {

	{ .fw_name = "bi_tcxo" },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map disp_cc_parent_map_1[] = {

	{ P_BI_TCXO, 0 },

	{ P_DP_PHY_PLL_LINK_CLK, 1 },

	{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data disp_cc_parent_data_1[] = {

	{ .fw_name = "bi_tcxo" },

	{ .fw_name = "dp_phy_pll_link_clk" },

	{ .fw_name = "dp_phy_pll_vco_div_clk" },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map disp_cc_parent_map_2[] = {

	{ P_BI_TCXO, 0 },

	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data disp_cc_parent_data_2[] = {

	{ .fw_name = "bi_tcxo" },

	{ .fw_name = "dsi0_phy_pll_out_byteclk" },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map disp_cc_parent_map_3[] = {
@@ -115,7 +109,6 @@ static const struct parent_map disp_cc_parent_map_3[] = { 
	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },

	{ P_GPLL0_OUT_MAIN, 4 },

	{ P_DISP_CC_PLL0_OUT_EVEN, 5 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data disp_cc_parent_data_3[] = {
@@ -123,31 +116,26 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = { 
	{ .hw = &disp_cc_pll0.clkr.hw },

	{ .fw_name = "gcc_disp_gpll0_clk_src" },

	{ .hw = &disp_cc_pll0_out_even.clkr.hw },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map disp_cc_parent_map_4[] = {

	{ P_BI_TCXO, 0 },

	{ P_GPLL0_OUT_MAIN, 4 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data disp_cc_parent_data_4[] = {

	{ .fw_name = "bi_tcxo" },

	{ .fw_name = "gcc_disp_gpll0_clk_src" },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct parent_map disp_cc_parent_map_5[] = {

	{ P_BI_TCXO, 0 },

	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const struct clk_parent_data disp_cc_parent_data_5[] = {

	{ .fw_name = "bi_tcxo" },

	{ .fw_name = "dsi0_phy_pll_out_dsiclk" },

	{ .fw_name = "core_bi_pll_test_se" },

};



static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
@@ -166,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_ahb_clk_src",

		.parent_data = disp_cc_parent_data_4,

		.num_parents = 3,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

	},
@@ -180,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_byte0_clk_src",

		.parent_data = disp_cc_parent_data_2,

		.num_parents = 3,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_byte2_ops,

	},
@@ -213,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_crypto_clk_src",

		.parent_data = disp_cc_parent_data_1,

		.num_parents = 4,

		.num_parents = 3,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_byte2_ops,

	},
@@ -227,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_link_clk_src",

		.parent_data = disp_cc_parent_data_1,

		.num_parents = 4,

		.num_parents = 3,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_byte2_ops,

	},
@@ -241,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_pixel_clk_src",

		.parent_data = disp_cc_parent_data_1,

		.num_parents = 4,

		.num_parents = 3,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_dp_ops,

	},
@@ -256,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_esc0_clk_src",

		.parent_data = disp_cc_parent_data_2,

		.num_parents = 3,

		.num_parents = 2,

		.ops = &clk_rcg2_ops,

	},

};
@@ -279,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_mdp_clk_src",

		.parent_data = disp_cc_parent_data_3,

		.num_parents = 5,

		.num_parents = 4,

		.ops = &clk_rcg2_shared_ops,

	},

};
@@ -292,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_pclk0_clk_src",

		.parent_data = disp_cc_parent_data_5,

		.num_parents = 3,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_pixel_ops,

	},
@@ -307,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_rot_clk_src",

		.parent_data = disp_cc_parent_data_3,

		.num_parents = 5,

		.num_parents = 4,

		.ops = &clk_rcg2_shared_ops,

	},

};
@@ -321,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_vsync_clk_src",

		.parent_data = disp_cc_parent_data_0,

		.num_parents = 2,

		.num_parents = 1,

		.ops = &clk_rcg2_shared_ops,

	},

};

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