dt-bindings: clocks: Convert Allwinner A80 DE clocks to a schema

# SPDX-License-Identifier: GPL-2.0+

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings

maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <mripard@kernel.org>

properties:

  "#clock-cells":

    const: 1

  "#reset-cells":

    const: 1

  compatible:

    const: allwinner,sun9i-a80-de-clks

  reg:

    maxItems: 1

  clocks:

    items:

      - description: Bus Clock

      - description: RAM Bus Clock

      - description: Module Clock

  clock-names:

    items:

      - const: mod

      - const: dram

      - const: bus

  resets:

    maxItems: 1

required:

  - "#clock-cells"

  - "#reset-cells"

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/sun9i-a80-ccu.h>

    #include <dt-bindings/reset/sun9i-a80-ccu.h>

    de_clocks: clock@3000000 {

        compatible = "allwinner,sun9i-a80-de-clks";

        reg = <0x03000000 0x30>;

        clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;

        clock-names = "mod", "dram", "bus";

        resets = <&ccu RST_BUS_DE>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

...

Allwinner A80 Display Engine Clock Control Binding

--------------------------------------------------

Required properties :

- compatible: must contain one of the following compatibles:

		- "allwinner,sun9i-a80-de-clks"

- reg: Must contain the registers base address and length

- clocks: phandle to the clocks feeding the display engine subsystem.

	  Three are needed:

  - "mod": the display engine module clock

  - "dram": the DRAM bus clock for the system

  - "bus": the bus clock for the whole display engine subsystem

- clock-names: Must contain the clock names described just above

- resets: phandle to the reset control for the display engine subsystem.

- #clock-cells : must contain 1

- #reset-cells : must contain 1

Example:

de_clocks: clock@3000000 {

	compatible = "allwinner,sun9i-a80-de-clks";

	reg = <0x03000000 0x30>;

	clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;

	clock-names = "mod", "dram", "bus";

	resets = <&ccu RST_BUS_DE>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};