arch/arm64/include/asm/memblock.h
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arch/arm64/mm/init.c
0 → 100644
+437
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arch/arm64/mm/mmu.c
0 → 100644
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This patch contains the initialisation of the memory blocks, MMU attributes and the memory map. Only five memory types are defined: Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable. Cache policies are supported via the memory attributes register (MAIR_EL1) and only affect the Normal Cacheable mappings. This patch also adds the SPARSEMEM_VMEMMAP initialisation. Signed-off-by:Will Deacon <will.deacon@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> Acked-by:
Tony Lindgren <tony@atomide.com> Acked-by:
Nicolas Pitre <nico@linaro.org> Acked-by:
Olof Johansson <olof@lixom.net> Acked-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Arnd Bergmann <arnd@arndb.de>
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