net: sgi: ioc3-eth: remove checkpatch errors/warning

/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.

// SPDX-License-Identifier: GPL-2.0

/* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.

 *

 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle

 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.

#include <linux/crc32.h>

#include <linux/mii.h>

#include <linux/in.h>

#include <linux/io.h>

#include <linux/ip.h>

#include <linux/tcp.h>

#include <linux/udp.h>

#include <net/ip.h>

#include <asm/byteorder.h>

#include <asm/io.h>

#include <asm/pgtable.h>

#include <linux/uaccess.h>

#include <asm/sn/types.h>

#include <asm/sn/ioc3.h>

#include <asm/pci/bridge.h>

/*

 * 64 RX buffers.  This is tunable in the range of 16 <= x < 512.  The

/* 64 RX buffers.  This is tunable in the range of 16 <= x < 512.  The

 * value must be a power of two.

 */

#define RX_BUFFS 64

	skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);

	if (likely(skb)) {

		int offset = aligned_rx_skb_addr((unsigned long)skb->data);

		if (offset)

			skb_reserve(skb, offset);

	}

}

/* BEWARE: The IOC3 documentation documents the size of rx buffers as

   1644 while it's actually 1664.  This one was nasty to track down ...  */

 * 1644 while it's actually 1664.  This one was nasty to track down ...

 */

#define RX_OFFSET		10

#define RX_BUF_ALLOC_SIZE	(1664 + RX_OFFSET + IOC3_CACHELINE)

/* DMA barrier to separate cached and uncached accesses.  */

#define BARRIER()							\

	__asm__("sync" ::: "memory")

#define IOC3_SIZE 0x100000

static inline u32 mcr_pack(u32 pulse, u32 sample)

	nic_wait(mcr);

}

/*

 * Read a byte from an iButton device

/* Read a byte from an iButton device

 */

static u32 nic_read_byte(u32 __iomem *mcr)

{

	return result;

}

/*

 * Write a byte to an iButton device

/* Write a byte to an iButton device

 */

static void nic_write_byte(u32 __iomem *mcr, int byte)

{

		b = nic_read_bit(mcr);

		if (a && b) {

			printk("NIC search failed (not fatal).\n");

			pr_warn("NIC search failed (not fatal).\n");

			*last = 0;

			return 0;

		}

			} else if (index > *last) {

				address &= ~(1UL << index);

				disc = index;

			} else if ((address & (1UL << index)) == 0)

			} else if ((address & (1UL << index)) == 0) {

				disc = index;

			}

			nic_write_bit(mcr, address & (1UL << index));

			continue;

		} else {

	while (1) {

		u64 reg;

		reg = nic_find(mcr, &save);

		switch (reg & 0xff) {

		break;

	}

	printk("Found %s NIC", type);

	pr_info("Found %s NIC", type);

	if (type != unknown)

		printk (" registration number %pM, CRC %02x", serial, crc);

	printk(".\n");

		pr_cont(" registration number %pM, CRC %02x", serial, crc);

	pr_cont(".\n");

	return 0;

}

/*

 * Read the NIC (Number-In-a-Can) device used to store the MAC address on

/* Read the NIC (Number-In-a-Can) device used to store the MAC address on

 * SN0 / SN00 nodeboards and PCI cards.

 */

static void ioc3_get_eaddr_nic(struct ioc3_private *ip)

	}

	if (tries < 0) {

		printk("Failed to read MAC address\n");

		pr_err("Failed to read MAC address\n");

		return;

	}

		ip->dev->dev_addr[i - 2] = nic[i];

}

/*

 * Ok, this is hosed by design.  It's necessary to know what machine the

/* Ok, this is hosed by design.  It's necessary to know what machine the

 * NIC is in in order to know how to read the NIC address.  We also have

 * to know if it's a PCI card or a NIC in on the node board ...

 */

{

	ioc3_get_eaddr_nic(ip);

	printk("Ethernet address is %pM.\n", ip->dev->dev_addr);

	pr_info("Ethernet address is %pM.\n", ip->dev->dev_addr);

}

static void __ioc3_set_mac_address(struct net_device *dev)

	return 0;

}

/*

 * Caller must hold the ioc3_lock ever for MII readers.  This is also

/* Caller must hold the ioc3_lock ever for MII readers.  This is also

 * used to protect the transmitter side but it's low contention.

 */

static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)

	return &dev->stats;

}

static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)

static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)

{

	struct ethhdr *eh = eth_hdr(skb);

	uint32_t csum, ehsum;

	unsigned int proto;

	struct iphdr *ih;

	uint16_t *ew;

	unsigned char *cp;

	struct iphdr *ih;

	u32 csum, ehsum;

	u16 *ew;

	/*

	 * Did hardware handle the checksum at all?  The cases we can handle

	/* Did hardware handle the checksum at all?  The cases we can handle

	 * are:

	 *

	 * - TCP and UDP checksums of IPv4 only.

	/* Same as tx - compute csum of pseudo header  */

	csum = hwsum +

	       (ih->tot_len - (ih->ihl << 2)) +

	       htons((uint16_t)ih->protocol) +

	       htons((u16)ih->protocol) +

	       (ih->saddr >> 16) + (ih->saddr & 0xffff) +

	       (ih->daddr >> 16) + (ih->daddr & 0xffff);

	/* Sum up ethernet dest addr, src addr and protocol  */

	ew = (uint16_t *) eh;

	ew = (u16 *)eh;

	ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];

	ehsum = (ehsum & 0xffff) + (ehsum >> 16);

	csum += 0xffff ^ ehsum;

	/* In the next step we also subtract the 1's complement

	   checksum of the trailing ethernet CRC.  */

	 * checksum of the trailing ethernet CRC.

	 */

	cp = (char *)eh + len;	/* points at trailing CRC */

	if (len & 1) {

		csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);

		csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);

		csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]);

		csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]);

	} else {

		csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);

		csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);

		csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]);

		csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]);

	}

	csum = (csum & 0xffff) + (csum >> 16);

			new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);

			if (!new_skb) {

				/* Ouch, drop packet and just recycle packet

				   to keep the ring filled.  */

				 * to keep the ring filled.

				 */

				dev->stats.rx_dropped++;

				new_skb = skb;

				goto next;

			if (likely(dev->features & NETIF_F_RXCSUM))

				ioc3_tcpudp_checksum(skb,

					w0 & ERXBUF_IPCKSUM_MASK, len);

						     w0 & ERXBUF_IPCKSUM_MASK,

						     len);

			netif_rx(skb);

			dev->stats.rx_bytes += len;

		} else {

			/* The frame is invalid and the skb never

			   reached the network layer so we can just

			   recycle it.  */

			 * reached the network layer so we can just

			 * recycle it.

			 */

			new_skb = skb;

			dev->stats.rx_errors++;

		}

	spin_unlock(&ip->ioc3_lock);

}

/*

 * Deal with fatal IOC3 errors.  This condition might be caused by a hard or

/* Deal with fatal IOC3 errors.  This condition might be caused by a hard or

 * software problems, so we should try to recover

 * more gracefully if this ever happens.  In theory we might be flooded

 * with such error interrupts if something really goes wrong, so we might

static void ioc3_error(struct net_device *dev, u32 eisr)

{

	struct ioc3_private *ip = netdev_priv(dev);

	unsigned char *iface = dev->name;

	spin_lock(&ip->ioc3_lock);

	if (eisr & EISR_RXOFLO)

		printk(KERN_ERR "%s: RX overflow.\n", iface);

		net_err_ratelimited("%s: RX overflow.\n", dev->name);

	if (eisr & EISR_RXBUFOFLO)

		printk(KERN_ERR "%s: RX buffer overflow.\n", iface);

		net_err_ratelimited("%s: RX buffer overflow.\n", dev->name);

	if (eisr & EISR_RXMEMERR)

		printk(KERN_ERR "%s: RX PCI error.\n", iface);

		net_err_ratelimited("%s: RX PCI error.\n", dev->name);

	if (eisr & EISR_RXPARERR)

		printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);

		net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name);

	if (eisr & EISR_TXBUFUFLO)

		printk(KERN_ERR "%s: TX buffer underflow.\n", iface);

		net_err_ratelimited("%s: TX buffer underflow.\n", dev->name);

	if (eisr & EISR_TXMEMERR)

		printk(KERN_ERR "%s: TX PCI error.\n", iface);

		net_err_ratelimited("%s: TX PCI error.\n", dev->name);

	ioc3_stop(ip);

	ioc3_init(dev);

}

/* The interrupt handler does all of the Rx thread work and cleans up

   after the Tx thread.  */

 * after the Tx thread.

 */

static irqreturn_t ioc3_interrupt(int irq, void *dev_id)

{

	struct ioc3_private *ip = netdev_priv(dev_id);

	add_timer(&ip->ioc3_timer);

}

/*

 * Try to find a PHY.  There is no apparent relation between the MII addresses

/* Try to find a PHY.  There is no apparent relation between the MII addresses

 * in the SGI documentation and what we find in reality, so we simply probe

 * for the PHY.  It seems IOC3 PHYs usually live on address 31.  One of my

 * onboard IOC3s has the special oddity that probing doesn't seem to find it

 */

static int ioc3_mii_init(struct ioc3_private *ip)

{

	int i, found = 0, res = 0;

	int ioc3_phy_workaround = 1;

	int i, found = 0, res = 0;

	u16 word;

	for (i = 0; i < 32; i++) {

	}

	if (!found) {

		if (ioc3_phy_workaround)

		if (ioc3_phy_workaround) {

			i = 31;

		else {

		} else {

			ip->mii.phy_id = -1;

			res = -ENODEV;

			goto out;

static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)

{

	struct ioc3_erxbuf *rxb;

	struct sk_buff *skb;

	int i;

	ip->rx_ci &= 511;

	for (i = ip->rx_ci; i != ip->rx_pi; i = (i + 1) & 511) {

		struct ioc3_erxbuf *rxb;

		skb = ip->rx_skbs[i];

		rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);

		rxb->w0 = 0;

	unsigned long *rxr;

	int i;

	if (ip->rxr == NULL) {

	if (!ip->rxr) {

		/* Allocate and initialize rx ring.  4kb = 512 entries  */

		ip->rxr = (unsigned long *)get_zeroed_page(GFP_ATOMIC);

		rxr = ip->rxr;

		if (!rxr)

			printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");

			pr_err("%s: get_zeroed_page() failed!\n", __func__);

		/* Now the rx buffers.  The RX ring may be larger but

		   we only allocate 16 buffers for now.  Need to tune

		   this for performance and memory later.  */

		 * we only allocate 16 buffers for now.  Need to tune

		 * this for performance and memory later.

		 */

		for (i = 0; i < RX_BUFFS; i++) {

			struct sk_buff *skb;

		ip->rx_pi = RX_BUFFS;

	}

	if (ip->txr == NULL) {

	if (!ip->txr) {

		/* Allocate and initialize tx rings.  16kb = 128 bufs.  */

		ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);

		if (!ip->txr)

			printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");

			pr_err("%s: __get_free_pages() failed!\n", __func__);

		ip->tx_pi = 0;

		ip->tx_ci = 0;

	}

	struct ioc3_private *ip = netdev_priv(dev);

	if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {

		printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);

		netdev_err(dev, "Can't get irq %d\n", dev->irq);

		return -EAGAIN;

	}

	return 0;

}

/*

 * MENET cards have four IOC3 chips, which are attached to two sets of

/* MENET cards have four IOC3 chips, which are attached to two sets of

 * PCI slot resources each: the primary connections are on slots

 * 0..3 and the secondaries are on 4..7

 *

static int ioc3_is_menet(struct pci_dev *pdev)

{

	return pdev->bus->parent == NULL &&

	return !pdev->bus->parent &&

	       ioc3_adjacent_is_ioc3(pdev, 0) &&

	       ioc3_adjacent_is_ioc3(pdev, 1) &&

	       ioc3_adjacent_is_ioc3(pdev, 2);

}

#ifdef CONFIG_SERIAL_8250

/*

 * Note about serial ports and consoles:

/* Note about serial ports and consoles:

 * For console output, everyone uses the IOC3 UARTA (offset 0x178)

 * connected to the master node (look in ip27_setup_console() and

 * ip27prom_console_write()).

{

	u32 sio_iec;

	/*

	 * We need to recognice and treat the fourth MENET serial as it

	/* We need to recognice and treat the fourth MENET serial as it

	 * does not have an SuperIO chip attached to it, therefore attempting

	 * to access it will result in bus errors.  We call something an

	 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3

	if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)

		return;

	/*

	 * Switch IOC3 to PIO mode.  It probably already was but let's be

	/* Switch IOC3 to PIO mode.  It probably already was but let's be

	 * paranoid

	 */

	writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL, &ioc3->gpcr_s);

		pci_using_dac = 1;

		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));

		if (err < 0) {

			printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "

			       "for consistent allocations\n", pci_name(pdev));

			pr_err("%s: Unable to obtain 64 bit DMA for consistent allocations\n",

			       pci_name(pdev));

			goto out;

		}

	} else {

		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));

		if (err) {

			printk(KERN_ERR "%s: No usable DMA configuration, "

			       "aborting.\n", pci_name(pdev));

			pr_err("%s: No usable DMA configuration, aborting.\n",

			       pci_name(pdev));

			goto out;

		}

		pci_using_dac = 0;

	ioc3_size = pci_resource_len(pdev, 0);

	ioc3 = (struct ioc3 *)ioremap(ioc3_base, ioc3_size);

	if (!ioc3) {

		printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",

		pr_err("ioc3eth(%s): ioremap failed, goodbye.\n",

		       pci_name(pdev));

		err = -ENOMEM;

		goto out_res;

	ioc3_mii_init(ip);

	if (ip->mii.phy_id == -1) {

		printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",

		pr_err("ioc3-eth(%s): Didn't find a PHY, goodbye.\n",

		       pci_name(pdev));

		err = -ENODEV;

		goto out_stop;

	vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);

	model  = (sw_physid2 >> 4) & 0x3f;

	rev    = sw_physid2 & 0xf;

	printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "

	       "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);

	printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,

	netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n",

		    ip->mii.phy_id, vendor, model, rev);

	netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n",

		    ip->emcr & EMCR_BUFSIZ ? 128 : 64);

	return 0;

out_free:

	free_netdev(dev);

out_disable:

	/*

	 * We should call pci_disable_device(pdev); here if the IOC3 wasn't

	/* We should call pci_disable_device(pdev); here if the IOC3 wasn't

	 * such a weird device ...

	 */

out:

	iounmap(ip->all_regs);

	pci_release_regions(pdev);

	free_netdev(dev);

	/*

	 * We should call pci_disable_device(pdev); here if the IOC3 wasn't

	/* We should call pci_disable_device(pdev); here if the IOC3 wasn't

	 * such a weird device ...

	 */

}

	struct ioc3_etxd *desc;

	unsigned long data;

	unsigned int len;

	uint32_t w0 = 0;

	int produce;

	u32 w0 = 0;

	/*

	 * IOC3 has a fairly simple minded checksumming hardware which simply

	/* IOC3 has a fairly simple minded checksumming hardware which simply

	 * adds up the 1's complement checksum for the entire packet and

	 * inserts it at an offset which can be specified in the descriptor

	 * into the transmit packet.  This means we have to compensate for the

		const struct iphdr *ih = ip_hdr(skb);

		const int proto = ntohs(ih->protocol);

		unsigned int csoff;

		uint32_t csum, ehsum;

		uint16_t *eh;

		u32 csum, ehsum;

		u16 *eh;

		/* The MAC header.  skb->mac seem the logic approach

		   to find the MAC header - except it's a NULL pointer ...  */

		eh = (uint16_t *) skb->data;

		 * to find the MAC header - except it's a NULL pointer ...

		 */

		eh = (u16 *)skb->data;

		/* Sum up dest addr, src addr and protocol  */

		ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];

		ehsum = (ehsum & 0xffff) + (ehsum >> 16);

		/* Skip IP header; it's sum is always zero and was

		   already filled in by ip_output.c */

		 * already filled in by ip_output.c

		 */

		csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,

					  ih->tot_len - (ih->ihl << 2),

					  proto, 0xffff ^ ehsum);

		desc->p1     = cpu_to_be64(ioc3_map(skb->data, 1));

	}

	BARRIER();

	mb(); /* make sure all descriptor changes are visible */

	ip->tx_skbs[produce] = skb;			/* Remember skb */

	produce = (produce + 1) & 127;

{

	struct ioc3_private *ip = netdev_priv(dev);

	printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);

	netdev_err(dev, "transmit timed out, resetting\n");

	spin_lock_irq(&ip->ioc3_lock);

	netif_wake_queue(dev);

}

/*

 * Given a multicast ethernet address, this routine calculates the

/* Given a multicast ethernet address, this routine calculates the

 * address's bit index in the logical address filter mask

 */

static inline unsigned int ioc3_hash(const unsigned char *addr)

{

	unsigned int temp = 0;

	u32 crc;

	int bits;

	u32 crc;

	crc = ether_crc_le(ETH_ALEN, addr);

		if ((dev->flags & IFF_ALLMULTI) ||

		    (netdev_mc_count(dev) > 64)) {

			/* Too many for hashing to make sense or we want all

			   multicast packets anyway,  so skip computing all the

			   hashes and just accept all packets.  */

			 * multicast packets anyway,  so skip computing all the

			 * hashes and just accept all packets.

			 */

			ip->ehar_h = 0xffffffff;

			ip->ehar_l = 0xffffffff;

		} else {