Commit c1b5371b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: cpg-mssr: Always use readl()/writel() 



The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel()
and readl()/writel() to access the clock registers. Settle on the
generic readl()/writel().

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 878f8baa

drivers/clk/renesas/renesas-cpg-mssr.c

+4 −5
Original line number Diff line number Diff line
@@ -146,12 +146,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 
		enable ? "ON" : "OFF");

	spin_lock_irqsave(&priv->mstp_lock, flags);



	value = clk_readl(priv->base + SMSTPCR(reg));

	value = readl(priv->base + SMSTPCR(reg));

	if (enable)

		value &= ~bitmask;

	else

		value |= bitmask;

	clk_writel(value, priv->base + SMSTPCR(reg));

	writel(value, priv->base + SMSTPCR(reg));



	spin_unlock_irqrestore(&priv->mstp_lock, flags);
@@ -159,8 +159,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 
		return 0;



	for (i = 1000; i > 0; --i) {

		if (!(clk_readl(priv->base + MSTPSR(reg)) &

		      bitmask))

		if (!(readl(priv->base + MSTPSR(reg)) & bitmask))

			break;

		cpu_relax();

	}
@@ -190,7 +189,7 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 
	struct cpg_mssr_priv *priv = clock->priv;

	u32 value;



	value = clk_readl(priv->base + MSTPSR(clock->index / 32));

	value = readl(priv->base + MSTPSR(clock->index / 32));



	return !(value & BIT(clock->index % 32));

}

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