Merge remote-tracking branch 'drm/drm-next' into drm-misc-next (c1b164a5) · Commits · 戴 / test

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt

+1 −0

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		@@ -7,6 +7,7 @@ output bus.

		Required properties:
		- compatible: "mediatek,<chip>-dpi"
		the supported chips are mt2701 , mt8173 and mt8183.
		- reg: Physical base address and length of the controller's registers
		- interrupts: The interrupt signal from the function block.
		- clocks: device clocks

+4 −4

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		@@ -207,10 +207,10 @@ DPIO
		CSR firmware support for DMC
		----------------------------

		.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
		.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
		:doc: csr support for dmc

		.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c
		.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
		:internal:

		Video BIOS Table (VBT)
		@@ -332,7 +332,7 @@ This process is dubbed relocation.
		GEM BO Management Implementation Details
		----------------------------------------

		.. kernel-doc:: drivers/gpu/drm/i915/i915_vma.h
		.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
		:doc: Virtual Memory Address

		Buffer Object Eviction
		@@ -382,7 +382,7 @@ Logical Rings, Logical Ring Contexts and Execlists
		Global GTT views
		----------------

		.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
		.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
		:doc: Global GTT views

		.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c

+1 −1

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		@@ -5629,7 +5629,7 @@ F: include/uapi/drm/lima_drm.h
		T: git git://anongit.freedesktop.org/drm/drm-misc

		DRM DRIVERS FOR MEDIATEK
		M: CK Hu <ck.hu@mediatek.com>
		M: Chun-Kuang Hu <chunkuang.hu@kernel.org>
		M: Philipp Zabel <p.zabel@pengutronix.de>
		L: dri-devel@lists.freedesktop.org
		S: Supported

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		# SPDX-License-Identifier: MIT
		menu "ACP (Audio CoProcessor) Configuration"
		depends on DRM_AMDGPU

		config DRM_AMD_ACP
		bool "Enable AMD Audio CoProcessor IP support"

+2 −0

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		@@ -994,6 +994,8 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
		uint32_t acc_flags);
		void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
		uint32_t acc_flags);
		void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
		uint32_t acc_flags);
		void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
		uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);