Commit c1aa81da authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Greg Kroah-Hartman
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parent cd7da3bc
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@@ -134,7 +134,7 @@ struct dwc2_hsotg_req;
 * @target_frame: Targeted frame num to setup next ISOC transfer
 * @frame_overrun: Indicates SOF number overrun in DSTS
 *
 * This is the driver's state for each registered enpoint, allowing it
 * This is the driver's state for each registered endpoint, allowing it
 * to keep track of transactions that need doing. Each endpoint has a
 * lock to protect the state, to try and avoid using an overall lock
 * for the host controller as much as possible.
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@@ -333,8 +333,8 @@ struct qe_udc {
	u32 resume_state;       /* USB state to resume*/
	u32 usb_state;          /* USB current state */
	u32 usb_next_state;     /* USB next state */
	u32 ep0_state;          /* Enpoint zero state */
	u32 ep0_dir;            /* Enpoint zero direction: can be
	u32 ep0_state;          /* Endpoint zero state */
	u32 ep0_dir;            /* Endpoint zero direction: can be
				USB_DIR_IN or USB_DIR_OUT*/
	u32 usb_sof_count;      /* SOF count */
	u32 errors;             /* USB ERRORs count */
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@@ -138,7 +138,7 @@ struct mv_u3d_op_regs {
	u32	doorbell;	/* doorbell register */
};

/* control enpoint enable registers */
/* control endpoint enable registers */
struct epxcr {
	u32	epxoutcr0;	/* ep out control 0 register */
	u32	epxoutcr1;	/* ep out control 1 register */
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@@ -1315,7 +1315,7 @@ done:
}

/*
 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
 * Set or clear the halt bit of an endpoint. A halted endpoint won't tx/rx any
 * data but will queue requests.
 *
 * exported to ep0 code