Commit c1701391 authored Mar 25, 2020 by Tomi Valkeinen Committed by Mauro Carvalho Chehab Apr 14, 2020

media: ti-vpe: cal: improve wait for CIO resetdone



Sometimes there is a timeout when waiting for the 'ComplexIO Reset
Done'.  Testing shows that sometimes we need to wait more than what the
current code does. It is not clear how long this wait can be, but it is
based on how quickly the sensor provides a valid clock, and how quickly
CAL syncs to it.

Change the code to make it more obvious how long we'll wait, and set a
wider range for usleep_range. Increase the timeout to 750ms.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

parent cbdda28a

drivers/media/platform/ti-vpe/cal.c

+4 −3

Original line number	Diff line number	Diff line
		@@ -825,15 +825,16 @@ static void csi2_phy_init(struct cal_ctx *ctx)

		static void csi2_wait_complexio_reset(struct cal_ctx *ctx)
		{
		int i;
		unsigned long timeout;

		for (i = 0; i < 250; i++) {
		timeout = jiffies + msecs_to_jiffies(750);
		while (time_before(jiffies, timeout)) {
		if (reg_read_field(ctx->dev,
		CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
		CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
		CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
		break;
		usleep_range(1000, 1100);
		usleep_range(500, 5000);
		}

		if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),

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