Commit c157863d authored by Jes Sorensen's avatar Jes Sorensen Committed by Kalle Valo
Browse files

rtl8xxxu: Reorder parts of init code to match the 8192eu vendor code flow



In order to debug 8192eu support, reorder some init code to match the
flow of the vendor driver.

Signed-off-by: default avatarJes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 85abfb12
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+20 −15
Original line number Diff line number Diff line
@@ -7592,6 +7592,26 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
	if (ret)
		goto exit;

	/* RFSW Control - clear bit 14 ?? */
	if (priv->rtl_chip != RTL8723B)
		rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
	/* 0x07000760 */
	if (priv->rtl_chip == RTL8192E) {
		val32 = 0;
	} else {
		val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
			FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
			((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
			 FPGA0_RF_BD_CTRL_SHIFT);
	}
	rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
	/* 0x860[6:5]= 00 - why? - this sets antenna B */
	if (priv->rtl_chip != RTL8192E)
		rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);

	priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
						  RF6052_REG_MODE_AG);

	/*
	 * Chip specific quirks
	 */
@@ -7653,21 +7673,6 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
	if (ret)
		goto exit;

	/* RFSW Control - clear bit 14 ?? */
	if (priv->rtl_chip != RTL8723B)
		rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
	/* 0x07000760 */
	val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
		FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
		((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
		 FPGA0_RF_BD_CTRL_SHIFT);
	rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
	/* 0x860[6:5]= 00 - why? - this sets antenna B */
	rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);

	priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
						  RF6052_REG_MODE_AG);

	/*
	 * Set RX page boundary
	 */