Commit c111e8bf authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branches 'pci/host', 'pci/host-designware', 'pci/host-hisi',... 

Merge branches 'pci/host', 'pci/host-designware', 'pci/host-hisi', 'pci/host-qcom' and 'pci/host-rcar' into next

* pci/host:
  PCI: host: Add of_pci_get_host_bridge_resources() stub
  PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD

* pci/host-designware:
  PCI: designware: Make config accessor override checking symmetric
  PCI: designware: Simplify control flow

* pci/host-hisi:
  PCI: hisi: Add support for HiSilicon Hip06 PCIe host controllers

* pci/host-qcom:
  ARM: dts: ifc6410: enable PCIe DT node for this board
  ARM: dts: apq8064: add PCIe devicetree node
  PCI: qcom: Add Qualcomm PCIe controller driver
  PCI: qcom: Document PCIe devicetree bindings
  PCI: designware: Ensure ATU is enabled before IO/conf space accesses

* pci/host-rcar:
  PCI: rcar: Add Gen2 PHY setup to pcie-rcar
  PCI: rcar: Add runtime PM support to pcie-rcar
  PCI: rcar: Remove unused pci_sys_data struct from pcie-rcar
parents 65d5b109 40704b12 67de2dc3 5930fe4e 668f4729 581d9434

Documentation/devicetree/bindings/pci/hisilicon-pcie.txt

+4 −4
Original line number Diff line number Diff line 
HiSilicon PCIe host bridge DT description

HiSilicon Hip05 and Hip06 PCIe host bridge DT description



HiSilicon PCIe host controller is based on Designware PCI core.

It shares common functions with PCIe Designware core driver and inherits
@@ -7,8 +7,8 @@ Documentation/devicetree/bindings/pci/designware-pci.txt. 


Additional properties are described here:



Required properties:

- compatible: Should contain "hisilicon,hip05-pcie".

Required properties

- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".

- reg: Should contain rc_dbi, config registers location and length.

- reg-names: Must include the following entries:

  "rc_dbi": controller configuration registers;
@@ -20,7 +20,7 @@ Optional properties: 
- status: Either "ok" or "disabled".

- dma-coherent: Present if DMA operations are coherent.



Example:

Hip05 Example (note that Hip06 is the same except compatible):

	pcie@0xb0080000 {

		compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";

		reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;

Documentation/devicetree/bindings/pci/qcom,pcie.txt

0 → 100644
+233 −0
Original line number Diff line number Diff line 
* Qualcomm PCI express root complex



- compatible:

	Usage: required

	Value type: <stringlist>

	Definition: Value should contain

			- "qcom,pcie-ipq8064" for ipq8064

			- "qcom,pcie-apq8064" for apq8064

			- "qcom,pcie-apq8084" for apq8084



- reg:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: Register ranges as listed in the reg-names property



- reg-names:

	Usage: required

	Value type: <stringlist>

	Definition: Must include the following entries

			- "parf"   Qualcomm specific registers

			- "dbi"	   Designware PCIe registers

			- "elbi"   External local bus interface registers

			- "config" PCIe configuration space



- device_type:

	Usage: required

	Value type: <string>

	Definition: Should be "pci". As specified in designware-pcie.txt



- #address-cells:

	Usage: required

	Value type: <u32>

	Definition: Should be 3. As specified in designware-pcie.txt



- #size-cells:

	Usage: required

	Value type: <u32>

	Definition: Should be 2. As specified in designware-pcie.txt



- ranges:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: As specified in designware-pcie.txt



- interrupts:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: MSI interrupt



- interrupt-names:

	Usage: required

	Value type: <stringlist>

	Definition: Should contain "msi"



- #interrupt-cells:

	Usage: required

	Value type: <u32>

	Definition: Should be 1. As specified in designware-pcie.txt



- interrupt-map-mask:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: As specified in designware-pcie.txt



- interrupt-map:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: As specified in designware-pcie.txt



- clocks:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: List of phandle and clock specifier pairs as listed

		    in clock-names property



- clock-names:

	Usage: required

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "iface"	Configuration AHB clock



- clock-names:

	Usage: required for ipq/apq8064

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "core"	Clocks the pcie hw block

			- "phy"		Clocks the pcie PHY block

- clock-names:

	Usage: required for apq8084

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary (AUX) clock

			- "bus_master"	Master AXI clock

			- "bus_slave"	Slave AXI clock

- resets:

	Usage: required

	Value type: <prop-encoded-array>

	Definition: List of phandle and reset specifier pairs as listed

		    in reset-names property



- reset-names:

	Usage: required for ipq/apq8064

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "axi"  AXI reset

			- "ahb"  AHB reset

			- "por"  POR reset

			- "pci"  PCI reset

			- "phy"  PHY reset



- reset-names:

	Usage: required for apq8084

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "core" Core reset



- power-domains:

	Usage: required for apq8084

	Value type: <prop-encoded-array>

	Definition: A phandle and power domain specifier pair to the

		    power domain which is responsible for collapsing

		    and restoring power to the peripheral



- vdda-supply:

	Usage: required

	Value type: <phandle>

	Definition: A phandle to the core analog power supply



- vdda_phy-supply:

	Usage: required for ipq/apq8064

	Value type: <phandle>

	Definition: A phandle to the analog power supply for PHY



- vdda_refclk-supply:

	Usage: required for ipq/apq8064

	Value type: <phandle>

	Definition: A phandle to the analog power supply for IC which generates

		    reference clock



- phys:

	Usage: required for apq8084

	Value type: <phandle>

	Definition: List of phandle(s) as listed in phy-names property



- phy-names:

	Usage: required for apq8084

	Value type: <stringlist>

	Definition: Should contain "pciephy"



- <name>-gpios:

	Usage: optional

	Value type: <prop-encoded-array>

	Definition: List of phandle and gpio specifier pairs. Should contain

			- "perst-gpios"	PCIe endpoint reset signal line

			- "wake-gpios"	PCIe endpoint wake signal line



* Example for ipq/apq8064

	pcie@1b500000 {

		compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";

		reg = <0x1b500000 0x1000

		       0x1b502000 0x80

		       0x1b600000 0x100

		       0x0ff00000 0x100000>;

		reg-names = "dbi", "elbi", "parf", "config";

		device_type = "pci";

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		num-lanes = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */

			  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */

		interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

				<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

				<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

		clocks = <&gcc PCIE_A_CLK>,

			 <&gcc PCIE_H_CLK>,

			 <&gcc PCIE_PHY_CLK>;

		clock-names = "core", "iface", "phy";

		resets = <&gcc PCIE_ACLK_RESET>,

			 <&gcc PCIE_HCLK_RESET>,

			 <&gcc PCIE_POR_RESET>,

			 <&gcc PCIE_PCI_RESET>,

			 <&gcc PCIE_PHY_RESET>;

		reset-names = "axi", "ahb", "por", "pci", "phy";

		pinctrl-0 = <&pcie_pins_default>;

		pinctrl-names = "default";

	};



* Example for apq8084

	pcie0@fc520000 {

		compatible = "qcom,pcie-apq8084", "snps,dw-pcie";

		reg = <0xfc520000 0x2000>,

		      <0xff000000 0x1000>,

		      <0xff001000 0x1000>,

		      <0xff002000 0x2000>;

		reg-names = "parf", "dbi", "elbi", "config";

		device_type = "pci";

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		num-lanes = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */

			  0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */

		interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

				<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

				<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

				<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

		clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,

			 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,

			 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,

			 <&gcc GCC_PCIE_0_AUX_CLK>;

		clock-names = "iface", "master_bus", "slave_bus", "aux";

		resets = <&gcc GCC_PCIE_0_BCR>;

		reset-names = "core";

		power-domains = <&gcc PCIE0_GDSC>;

		vdda-supply = <&pma8084_l3>;

		phys = <&pciephy0>;

		phy-names = "pciephy";

		perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;

		pinctrl-0 = <&pcie0_pins_default>;

		pinctrl-names = "default";

	};

MAINTAINERS

+8 −0
Original line number Diff line number Diff line
@@ -8240,11 +8240,19 @@ F: drivers/pci/host/pci-xgene-msi.c 


PCIE DRIVER FOR HISILICON

M:	Zhou Wang <wangzhou1@hisilicon.com>

M:	Gabriele Paoloni <gabriele.paoloni@huawei.com>

L:	linux-pci@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/hisilicon-pcie.txt

F:	drivers/pci/host/pcie-hisi.c



PCIE DRIVER FOR QUALCOMM MSM

M:     Stanimir Varbanov <svarbanov@mm-sol.com>

L:     linux-pci@vger.kernel.org

L:     linux-arm-msm@vger.kernel.org

S:     Maintained

F:     drivers/pci/host/*qcom*



PCMCIA SUBSYSTEM

P:	Linux PCMCIA Team

L:	linux-pcmcia@lists.infradead.org

arch/arm/boot/dts/qcom-apq8064-ifc6410.dts

+26 −0
Original line number Diff line number Diff line
@@ -47,6 +47,18 @@ 
					bias-disable;

				};

			};



			pcie_pins: pcie_pinmux {

				mux {

					pins = "gpio27";

					function = "gpio";

				};

				conf {

					pins = "gpio27";

					drive-strength = <12>;

					bias-disable;

				};

			};

		};



		rpm@108000 {
@@ -123,6 +135,10 @@ 
				pm8921_lvs1: lvs1 {

					bias-pull-down;

				};



				lvs6 {

					bias-pull-down;

				};

			};

		};
@@ -231,6 +247,16 @@ 
			status = "okay";

		};



		pci@1b500000 {

			status = "ok";

			vdda-supply = <&pm8921_s3>;

			vdda_phy-supply = <&pm8921_lvs6>;

			vdda_refclk-supply = <&ext_3p3v>;

			pinctrl-0 = <&pcie_pins>;

			pinctrl-names = "default";

			perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;

		};



		qcom,ssbi@500000 {

			pmic@0 {

				gpio@150 {

arch/arm/boot/dts/qcom-apq8064.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -659,5 +659,41 @@ 
			compatible = "qcom,tcsr-apq8064", "syscon";

			reg = <0x1a400000 0x100>;

		};



		pcie: pci@1b500000 {

			compatible = "qcom,pcie-apq8064", "snps,dw-pcie";

			reg = <0x1b500000 0x1000

			       0x1b502000 0x80

			       0x1b600000 0x100

			       0x0ff00000 0x100000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;

			ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */

				  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */

			interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc PCIE_A_CLK>,

				 <&gcc PCIE_H_CLK>,

				 <&gcc PCIE_PHY_REF_CLK>;

			clock-names = "core", "iface", "phy";

			resets = <&gcc PCIE_ACLK_RESET>,

				 <&gcc PCIE_HCLK_RESET>,

				 <&gcc PCIE_POR_RESET>,

				 <&gcc PCIE_PCI_RESET>,

				 <&gcc PCIE_PHY_RESET>;

			reset-names = "axi", "ahb", "por", "pci", "phy";

			status = "disabled";

		};

	};

};

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