drm/amd/display: setup system context in dm_init

	}

}

static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)

{

	uint64_t pt_base;

	uint32_t logical_addr_low;

	uint32_t logical_addr_high;

	uint32_t agp_base, agp_bot, agp_top;

	PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;

	logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;

	pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

	if (adev->apu_flags & AMD_APU_IS_RAVEN2)

		/*

		 * Raven2 has a HW issue that it is unable to use the vram which

		 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the

		 * workaround that increase system aperture high address (add 1)

		 * to get rid of the VM fault and hardware hang.

		 */

		logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);

	else

		logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;

	agp_base = 0;

	agp_bot = adev->gmc.agp_start >> 24;

	agp_top = adev->gmc.agp_end >> 24;

	page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;

	page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);

	page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;

	page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);

	page_table_base.high_part = upper_32_bits(pt_base) & 0xF;

	page_table_base.low_part = lower_32_bits(pt_base);

	pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;

	pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;

	pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;

	pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;

	pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;

	pa_config->system_aperture.fb_base = adev->gmc.fb_start;

	pa_config->system_aperture.fb_offset = adev->gmc.aper_base;

	pa_config->system_aperture.fb_top = adev->gmc.fb_end;

	pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;

	pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;

	pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;

	pa_config->is_hvm_enabled = 0;

}

static int amdgpu_dm_init(struct amdgpu_device *adev)

{

	struct dc_init_data init_data;

#ifdef CONFIG_DRM_AMD_DC_HDCP

	struct dc_callback_init init_params;

#endif

	struct dc_phy_addr_space_config pa_config;

	int r;

	adev->dm.ddev = adev_to_drm(adev);

	dc_hardware_init(adev->dm.dc);

	mmhub_read_system_context(adev, &pa_config);

	// Call the DC init_memory func

	dc_setup_system_context(adev->dm.dc, &pa_config);

	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);

	if (!adev->dm.freesync_module) {

		DRM_ERROR(

		goto error;

	}

	DRM_DEBUG_DRIVER("KMS initialized.\n");

	return 0;