Commit c0ee0e43 authored by Marc Gonzalez's avatar Marc Gonzalez Committed by Stephen Boyd
Browse files

clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 



See similar issue solved by commit 5f2420ed
("clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998")

Without this patch, PCIe PHY init fails:

qcom-qmp-phy 1c06000.phy: pipe_clk enable failed err=-16
phy phy-1c06000.phy.0: phy init failed --> -16

Signed-off-by: default avatarMarc Gonzalez <marc.w.gonzalez@free.fr>
Reviewed-by: default avatarJeffrey Hugo <jhugo@codeaurora.org>
Fixes: b5f5f525 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 892df019

drivers/clk/qcom/gcc-msm8998.c

+1 −1
Original line number Diff line number Diff line
@@ -2161,7 +2161,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 


static struct clk_branch gcc_pcie_0_pipe_clk = {

	.halt_reg = 0x6b018,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x6b018,

		.enable_mask = BIT(0),

CRA Git | Maintained and supported by SUSTech CRA and CCSE