Commit c0d6fe2f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM DT updates from Olof Johansson:
 "As usual, this is the massive branch we have for each release.  Lots
  of various updates and additions of hardware descriptions on existing
  hardware, as well as the usual additions of new boards and SoCs.

  This is also the first release where we've started mixing 64- and
  32-bit DT updates in one branch.

  (Specific details on what's actually here and new is pretty easy to
  tell from the diffstat, so there's little point in duplicating listing
  it here)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (499 commits)
  ARM: dts: uniphier: add system-bus-controller nodes
  ARM64: juno: disable NOR flash node by default
  ARM: dts: uniphier: add outer cache controller nodes
  arm64: defconfig: Enable PCI generic host bridge by default
  arm64: Juno: Add support for the PCIe host bridge on Juno R1
  Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
  ARM: dts: uniphier: add I2C aliases for ProXstream2 boards
  dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
  dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
  dts/ls2080a: Update Simulator DTS to add support of various peripherals
  dts/ls2080a: Remove text about writing to Free Software Foundation
  dts/ls2080a: Update DTSI to add support of various peripherals
  doc: DTS: Update DWC3 binding to provide reference to generic bindings
  doc/bindings: Update GPIO devicetree binding documentation for LS2080A
  Documentation/dts: Move FSL board-specific bindings out of /powerpc
  Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
  arm64: Rename FSL LS2085A SoC support code to LS2080A
  arm64: Use generic Layerscape SoC family naming
  ARM: dts: uniphier: add ProXstream2 Vodka board support
  ARM: dts: uniphier: add ProXstream2 Gentil board support
  ...
parents b44a3d2a 3e4dda70

Documentation/devicetree/bindings/arm/amlogic.txt

+8 −2
Original line number Diff line number Diff line
@@ -9,6 +9,12 @@ Boards with the Amlogic Meson8 SoC shall have the following properties: 
  Required root node property:

    compatible: "amlogic,meson8";



Boards with the Amlogic Meson8b SoC shall have the following properties:

  Required root node property:

    compatible: "amlogic,meson8b";



Board compatible values:

  - "geniatech,atv1200"

  - "minix,neo-x8"
 
  - "geniatech,atv1200" (Meson6)

  - "minix,neo-x8" (Meson8)

  - "tronfy,mxq" (Meson8b)

  - "hardkernel,odroid-c1" (Meson8b)

Documentation/devicetree/bindings/arm/apm/scu.txt

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+17 −0
Original line number Diff line number Diff line 
APM X-GENE SoC series SCU Registers



This system clock unit contain various register that control block resets,

clock enable/disables, clock divisors and other deepsleep registers.



Properties:

 - compatible : should contain two values. First value must be:

		   - "apm,xgene-scu"

		second value must be always "syscon".



 - reg : offset and length of the register set.



Example :

	scu: system-clk-controller@17000000 {

		compatible = "apm,xgene-scu","syscon";

		reg = <0x0 0x17000000 0x0 0x400>;

	};

Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt

+160 −2
Original line number Diff line number Diff line
@@ -20,6 +20,25 @@ system control is required: 
    - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"

    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"



hif-cpubiuctrl node

-------------------

SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit

(BIU) block which controls and interfaces the CPU complex to the different

Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block

offers a feature called Write Pairing which consists in collapsing two adjacent

cache lines into a single (bursted) write transaction towards the memory

controller (MEMC) to maximize write bandwidth.



Required properties:



    - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"



Optional properties:



    - brcm,write-pairing:

	Boolean property, which when present indicates that the chip

	supports write-pairing.



example:

    rdb {

        #address-cells = <1>;
@@ -35,6 +54,7 @@ example: 
        hif_cpubiuctrl: syscon@3e2400 {

            compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";

            reg = <0x3e2400 0x5b4>;

            brcm,write-pairing;

        };



        hif_continuation: syscon@452000 {
@@ -43,8 +63,7 @@ example: 
        };

    };



Lastly, nodes that allow for support of SMP initialization and reboot are

required:

Nodes that allow for support of SMP initialization and reboot are required:



smpboot

-------
@@ -95,3 +114,142 @@ example: 
        compatible = "brcm,brcmstb-reboot";

        syscon = <&sun_top_ctrl 0x304 0x308>;

    };







Power management

----------------



For power management (particularly, S2/S3/S5 system suspend), the following SoC

components are needed:



= Always-On control block (AON CTRL)



This hardware provides control registers for the "always-on" (even in low-power

modes) hardware, such as the Power Management State Machine (PMSM).



Required properties:

- compatible     : should contain "brcm,brcmstb-aon-ctrl"

- reg            : the register start and length for the AON CTRL block



Example:



aon-ctrl@410000 {

	compatible = "brcm,brcmstb-aon-ctrl";

	reg = <0x410000 0x400>;

};



= Memory controllers



A Broadcom STB SoC typically has a number of independent memory controllers,

each of which may have several associated hardware blocks, which are versioned

independently (control registers, DDR PHYs, etc.). One might consider

describing these controllers as a parent "memory controllers" block, which

contains N sub-nodes (one for each controller in the system), each of which is

associated with a number of hardware register resources (e.g., its PHY). See

the example device tree snippet below.



== MEMC (MEMory Controller)



Represents a single memory controller instance.



Required properties:

- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"



Should contain subnodes for any of the following relevant hardware resources:



== DDR PHY control



Control registers for this memory controller's DDR PHY.



Required properties:

- compatible     : should contain one of these

	"brcm,brcmstb-ddr-phy-v225.1"

	"brcm,brcmstb-ddr-phy-v240.1"

	"brcm,brcmstb-ddr-phy-v240.2"



- reg            : the DDR PHY register range



== DDR SHIMPHY



Control registers for this memory controller's DDR SHIMPHY.



Required properties:

- compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"

- reg            : the DDR SHIMPHY register range



== MEMC DDR control



Sequencer DRAM parameters and control registers. Used for Self-Refresh

Power-Down (SRPD), among other things.



Required properties:

- compatible     : should contain "brcm,brcmstb-memc-ddr"

- reg            : the MEMC DDR register range



Example:



memory_controllers {

	ranges;

	compatible = "simple-bus";



	memc@0 {

		compatible = "brcm,brcmstb-memc", "simple-bus";

		ranges;



		ddr-phy@f1106000 {

			compatible = "brcm,brcmstb-ddr-phy-v240.1";

			reg = <0xf1106000 0x21c>;

		};



		shimphy@f1108000 {

			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";

			reg = <0xf1108000 0xe4>;

		};



		memc-ddr@f1102000 {

			reg = <0xf1102000 0x800>;

			compatible = "brcm,brcmstb-memc-ddr";

		};

	};



	memc@1 {

		compatible = "brcm,brcmstb-memc", "simple-bus";

		ranges;



		ddr-phy@f1186000 {

			compatible = "brcm,brcmstb-ddr-phy-v240.1";

			reg = <0xf1186000 0x21c>;

		};



		shimphy@f1188000 {

			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";

			reg = <0xf1188000 0xe4>;

		};



		memc-ddr@f1182000 {

			reg = <0xf1182000 0x800>;

			compatible = "brcm,brcmstb-memc-ddr";

		};

	};



	memc@2 {

		compatible = "brcm,brcmstb-memc", "simple-bus";

		ranges;



		ddr-phy@f1206000 {

			compatible = "brcm,brcmstb-ddr-phy-v240.1";

			reg = <0xf1206000 0x21c>;

		};



		shimphy@f1208000 {

			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";

			reg = <0xf1208000 0xe4>;

		};



		memc-ddr@f1202000 {

			reg = <0xf1202000 0x800>;

			compatible = "brcm,brcmstb-memc-ddr";

		};

	};

};

Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt

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+34 −0
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Broadcom Northstar Plus device tree bindings

--------------------------------------------



Broadcom Northstar Plus family of SoCs are used for switching control

and management applications as well as residential router/gateway

applications. The SoC features dual core Cortex A9 ARM CPUs, integrating

several peripheral interfaces including multiple Gigabit Ethernet PHYs,

DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,

SATA and several other IO controllers.



Boards with Northstar Plus SoCs shall have the following properties:



Required root node property:



BCM58522

compatible = "brcm,bcm58522", "brcm,nsp";



BCM58525

compatible = "brcm,bcm58525", "brcm,nsp";



BCM58535

compatible = "brcm,bcm58535", "brcm,nsp";



BCM58622

compatible = "brcm,bcm58622", "brcm,nsp";



BCM58623

compatible = "brcm,bcm58623", "brcm,nsp";



BCM58625

compatible = "brcm,bcm58625", "brcm,nsp";



BCM88312

compatible = "brcm,bcm88312", "brcm,nsp";

Documentation/devicetree/bindings/arm/cpus.txt

+2 −0
Original line number Diff line number Diff line
@@ -195,6 +195,8 @@ nodes to be present and contain the properties described below. 
			    "marvell,armada-380-smp"

			    "marvell,armada-390-smp"

			    "marvell,armada-xp-smp"

			    "mediatek,mt6589-smp"

			    "mediatek,mt81xx-tz-smp"

			    "qcom,gcc-msm8660"

			    "qcom,kpss-acc-v1"

			    "qcom,kpss-acc-v2"

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