Commit c0a51fd0 authored by Christian König's avatar Christian König Committed by Chris Wilson
Browse files

drm: move read_domains and write_domain into i915 



i915 is the only driver using those fields in the drm_gem_object
structure, so they only waste memory for all other drivers.

Move the fields into drm_i915_gem_object instead and patch the i915 code
with the following sed commands:

sed -i "s/obj->base.read_domains/obj->read_domains/g" drivers/gpu/drm/i915/*.c drivers/gpu/drm/i915/*/*.c
sed -i "s/obj->base.write_domain/obj->write_domain/g" drivers/gpu/drm/i915/*.c drivers/gpu/drm/i915/*/*.c

Change is only compile tested.

v2: move fields around as suggested by Chris.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180216124338.9087-1-christian.koenig@amd.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent e1039626

drivers/gpu/drm/i915/gvt/dmabuf.c

+2 −2
Original line number Diff line number Diff line
@@ -162,8 +162,8 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 
		info->size << PAGE_SHIFT);

	i915_gem_object_init(obj, &intel_vgpu_gem_ops);



	obj->base.read_domains = I915_GEM_DOMAIN_GTT;

	obj->base.write_domain = 0;

	obj->read_domains = I915_GEM_DOMAIN_GTT;

	obj->write_domain = 0;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		unsigned int tiling_mode = 0;

		unsigned int stride = 0;

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -150,8 +150,8 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 
		   get_global_flag(obj),

		   get_pin_mapped_flag(obj),

		   obj->base.size / 1024,

		   obj->base.read_domains,

		   obj->base.write_domain,

		   obj->read_domains,

		   obj->write_domain,

		   i915_cache_level_str(dev_priv, obj->cache_level),

		   obj->mm.dirty ? " dirty" : "",

		   obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");

drivers/gpu/drm/i915/i915_gem.c

+30 −30
Original line number Diff line number Diff line
@@ -240,8 +240,8 @@ err_phys: 


static void __start_cpu_write(struct drm_i915_gem_object *obj)

{

	obj->base.read_domains = I915_GEM_DOMAIN_CPU;

	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	obj->read_domains = I915_GEM_DOMAIN_CPU;

	obj->write_domain = I915_GEM_DOMAIN_CPU;

	if (cpu_write_needs_clflush(obj))

		obj->cache_dirty = true;

}
@@ -257,7 +257,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, 
		obj->mm.dirty = false;



	if (needs_clflush &&

	    (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&

	    (obj->read_domains & I915_GEM_DOMAIN_CPU) == 0 &&

	    !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))

		drm_clflush_sg(pages);
@@ -703,10 +703,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) 
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);

	struct i915_vma *vma;



	if (!(obj->base.write_domain & flush_domains))

	if (!(obj->write_domain & flush_domains))

		return;



	switch (obj->base.write_domain) {

	switch (obj->write_domain) {

	case I915_GEM_DOMAIN_GTT:

		i915_gem_flush_ggtt_writes(dev_priv);
@@ -731,7 +731,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) 
		break;

	}



	obj->base.write_domain = 0;

	obj->write_domain = 0;

}



static inline int
@@ -831,7 +831,7 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 
	 * anyway again before the next pread happens.

	 */

	if (!obj->cache_dirty &&

	    !(obj->base.read_domains & I915_GEM_DOMAIN_CPU))

	    !(obj->read_domains & I915_GEM_DOMAIN_CPU))

		*needs_clflush = CLFLUSH_BEFORE;



out:
@@ -890,7 +890,7 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, 
		 * Same trick applies to invalidate partially written

		 * cachelines read before writing.

		 */

		if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))

		if (!(obj->read_domains & I915_GEM_DOMAIN_CPU))

			*needs_clflush |= CLFLUSH_BEFORE;

	}
@@ -2391,8 +2391,8 @@ static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) 
	 * wasn't in the GTT, there shouldn't be any way it could have been in

	 * a GPU cache

	 */

	GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);

	GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);

	GEM_BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);

	GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);



	st = kmalloc(sizeof(*st), GFP_KERNEL);

	if (st == NULL)
@@ -3703,7 +3703,7 @@ static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj) 
	flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);

	if (obj->cache_dirty)

		i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);

	obj->base.write_domain = 0;

	obj->write_domain = 0;

}



void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
@@ -3740,7 +3740,7 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) 
	if (ret)

		return ret;



	if (obj->base.write_domain == I915_GEM_DOMAIN_WC)

	if (obj->write_domain == I915_GEM_DOMAIN_WC)

		return 0;



	/* Flush and acquire obj->pages so that we are coherent through
@@ -3761,17 +3761,17 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) 
	 * coherent writes from the GPU, by effectively invalidating the

	 * WC domain upon first access.

	 */

	if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0)

	if ((obj->read_domains & I915_GEM_DOMAIN_WC) == 0)

		mb();



	/* It should now be out of any other write domains, and we can update

	 * the domain values for our changes.

	 */

	GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0);

	obj->base.read_domains |= I915_GEM_DOMAIN_WC;

	GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_WC) != 0);

	obj->read_domains |= I915_GEM_DOMAIN_WC;

	if (write) {

		obj->base.read_domains = I915_GEM_DOMAIN_WC;

		obj->base.write_domain = I915_GEM_DOMAIN_WC;

		obj->read_domains = I915_GEM_DOMAIN_WC;

		obj->write_domain = I915_GEM_DOMAIN_WC;

		obj->mm.dirty = true;

	}
@@ -3803,7 +3803,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 
	if (ret)

		return ret;



	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)

	if (obj->write_domain == I915_GEM_DOMAIN_GTT)

		return 0;



	/* Flush and acquire obj->pages so that we are coherent through
@@ -3824,17 +3824,17 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 
	 * coherent writes from the GPU, by effectively invalidating the

	 * GTT domain upon first access.

	 */

	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)

	if ((obj->read_domains & I915_GEM_DOMAIN_GTT) == 0)

		mb();



	/* It should now be out of any other write domains, and we can update

	 * the domain values for our changes.

	 */

	GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);

	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;

	GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);

	obj->read_domains |= I915_GEM_DOMAIN_GTT;

	if (write) {

		obj->base.read_domains = I915_GEM_DOMAIN_GTT;

		obj->base.write_domain = I915_GEM_DOMAIN_GTT;

		obj->read_domains = I915_GEM_DOMAIN_GTT;

		obj->write_domain = I915_GEM_DOMAIN_GTT;

		obj->mm.dirty = true;

	}
@@ -4146,7 +4146,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 
	/* It should now be out of any other write domains, and we can update

	 * the domain values for our changes.

	 */

	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;

	obj->read_domains |= I915_GEM_DOMAIN_GTT;



	return vma;
@@ -4199,15 +4199,15 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) 
	flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);



	/* Flush the CPU cache if it's still invalid. */

	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {

	if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {

		i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);

		obj->base.read_domains |= I915_GEM_DOMAIN_CPU;

		obj->read_domains |= I915_GEM_DOMAIN_CPU;

	}



	/* It should now be out of any other write domains, and we can update

	 * the domain values for our changes.

	 */

	GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);

	GEM_BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU);



	/* If we're writing through the CPU, then the GPU read domains will

	 * need to be invalidated at next use.
@@ -4643,8 +4643,8 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) 


	i915_gem_object_init(obj, &i915_gem_object_ops);



	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	obj->base.read_domains = I915_GEM_DOMAIN_CPU;

	obj->write_domain = I915_GEM_DOMAIN_CPU;

	obj->read_domains = I915_GEM_DOMAIN_CPU;



	if (HAS_LLC(dev_priv))

		/* On some devices, we can have the GPU use the LLC (the CPU
@@ -5702,7 +5702,7 @@ i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, 
	if (IS_ERR(obj))

		return obj;



	GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);

	GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);



	file = obj->base.filp;

	offset = 0;

drivers/gpu/drm/i915/i915_gem_clflush.c

+1 −1
Original line number Diff line number Diff line
@@ -177,7 +177,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, 
	} else if (obj->mm.pages) {

		__i915_do_clflush(obj);

	} else {

		GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);

		GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);

	}



	obj->cache_dirty = false;

drivers/gpu/drm/i915/i915_gem_dmabuf.c

+2 −2
Original line number Diff line number Diff line
@@ -330,8 +330,8 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 
	 * write-combined buffer or a delay through the chipset for GTT

	 * writes that do require us to treat GTT as a separate cache domain.)

	 */

	obj->base.read_domains = I915_GEM_DOMAIN_GTT;

	obj->base.write_domain = 0;

	obj->read_domains = I915_GEM_DOMAIN_GTT;

	obj->write_domain = 0;



	return &obj->base;

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