Commit c02cc235 authored May 07, 2018 by Geert Uytterhoeven Committed by Simon Horman May 14, 2018

ARM: dts: r7s72100: Correct watchdog timer interrupt type



According to table 7.3 ("List of Interrupt IDs") in the RZ/A1H Hardware
User's Manual rev. 3.00, the watchdog timer interrupt is a level
interrupt.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

parent 7207b947

arch/arm/boot/dts/r7s72100.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -387,7 +387,7 @@
		wdt: watchdog@fcfe0000 {
		compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
		reg = <0xfcfe0000 0x6>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&p0_clk>;
		};

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