Commit c0275ae7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpu-features updates from Ingo Molnar:
 "The biggest change in this cycle was a large series from Sean
  Christopherson to clean up the handling of VMX features. This both
  fixes bugs/inconsistencies and makes the code more coherent and
  future-proof.

  There are also two cleanups and a minor TSX syslog messages
  enhancement"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
  x86/cpu: Remove redundant cpu_detect_cache_sizes() call
  x86/cpu: Print "VMX disabled" error message iff KVM is enabled
  KVM: VMX: Allow KVM_INTEL when building for Centaur and/or Zhaoxin CPUs
  perf/x86: Provide stubs of KVM helpers for non-Intel CPUs
  KVM: VMX: Use VMX_FEATURE_* flags to define VMCS control bits
  KVM: VMX: Check for full VMX support when verifying CPU compatibility
  KVM: VMX: Use VMX feature flag to query BIOS enabling
  KVM: VMX: Drop initialization of IA32_FEAT_CTL MSR
  x86/cpufeatures: Add flag to track whether MSR IA32_FEAT_CTL is configured
  x86/cpu: Set synthetic VMX cpufeatures during init_ia32_feat_ctl()
  x86/cpu: Print VMX flags in /proc/cpuinfo using VMX_FEATURES_*
  x86/cpu: Detect VMX features on Intel, Centaur and Zhaoxin CPUs
  x86/vmx: Introduce VMX_FEATURES_*
  x86/cpu: Clear VMX feature flag if VMX is not fully enabled
  x86/zhaoxin: Use common IA32_FEAT_CTL MSR initialization
  x86/centaur: Use common IA32_FEAT_CTL MSR initialization
  x86/mce: WARN once if IA32_FEAT_CTL MSR is left unlocked
  x86/intel: Initialize IA32_FEAT_CTL MSR at boot
  tools/x86: Sync msr-index.h from kernel sources
  selftests, kvm: Replace manual MSR defs with common msr-index.h
  ...
parents f6170f0a 283bab98

MAINTAINERS

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@@ -9171,7 +9171,7 @@ F: arch/x86/include/uapi/asm/svm.h 
F:	arch/x86/include/asm/kvm*

F:	arch/x86/include/asm/pvclock-abi.h

F:	arch/x86/include/asm/svm.h

F:	arch/x86/include/asm/vmx.h

F:	arch/x86/include/asm/vmx*.h

F:	arch/x86/kernel/kvm.c

F:	arch/x86/kernel/kvmclock.c

































arch/x86/Kconfig.cpu



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@@ -387,6 +387,14 @@ config X86_DEBUGCTLMSR













	def_bool y















	depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486SX || M486) && !UML





























config IA32_FEAT_CTL













	def_bool y













	depends on CPU_SUP_INTEL || CPU_SUP_CENTAUR || CPU_SUP_ZHAOXIN



























config X86_VMX_FEATURE_NAMES













	def_bool y













	depends on IA32_FEAT_CTL && X86_FEATURE_NAMES





























menuconfig PROCESSOR_SELECT















	bool "Supported processor vendors" if EXPERT















	---help---

































arch/x86/boot/mkcpustr.c



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@@ -15,6 +15,7 @@













#include "../include/asm/required-features.h"















#include "../include/asm/disabled-features.h"















#include "../include/asm/cpufeatures.h"













#include "../include/asm/vmxfeatures.h"















#include "../kernel/cpu/capflags.c"































int main(void)

































arch/x86/include/asm/cpufeatures.h



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@@ -220,6 +220,7 @@













#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */















#define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */















#define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */













#define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */































/* Virtualization flags: Linux defined, word 8 */















#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */

































arch/x86/include/asm/msr-index.h



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@@ -558,7 +558,14 @@













#define MSR_IA32_EBL_CR_POWERON		0x0000002a















#define MSR_EBC_FREQUENCY_ID		0x0000002c















#define MSR_SMI_COUNT			0x00000034













#define MSR_IA32_FEATURE_CONTROL        0x0000003a



























/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */













#define MSR_IA32_FEAT_CTL		0x0000003a













#define FEAT_CTL_LOCKED				BIT(0)













#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX		BIT(1)













#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX	BIT(2)













#define FEAT_CTL_LMCE_ENABLED			BIT(20)





























#define MSR_IA32_TSC_ADJUST             0x0000003b















#define MSR_IA32_BNDCFGS		0x00000d90

























@@ -566,11 +573,6 @@





























#define MSR_IA32_XSS			0x00000da0





























#define FEATURE_CONTROL_LOCKED				(1<<0)













#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)













#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)













#define FEATURE_CONTROL_LMCE				(1<<20)





























#define MSR_IA32_APICBASE		0x0000001b















#define MSR_IA32_APICBASE_BSP		(1<<8)















#define MSR_IA32_APICBASE_ENABLE	(1<<11)









































































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