dmaengine: pxa_dma: add debug information (c01d1b51) · Commits · 戴 / test

drivers/dma/pxa_dma.c

+244 −0

Original line number	Diff line number	Diff line
		@@ -125,6 +125,11 @@ struct pxad_device {
		void __iomem *base;
		struct pxad_phy *phys;
		spinlock_t phy_lock; /* Phy association */
		#ifdef CONFIG_DEBUG_FS
		struct dentry *dbgfs_root;
		struct dentry *dbgfs_state;
		struct dentry **dbgfs_chan;
		#endif
		};

		#define tx_to_pxad_desc(tx) \
		@@ -168,6 +173,243 @@ static unsigned int pxad_drcmr(unsigned int line)
		return 0x100 + line * 4;
		return 0x1000 + line * 4;
		}

		/*
		* Debug fs
		*/
		#ifdef CONFIG_DEBUG_FS
		#include <linux/debugfs.h>
		#include <linux/uaccess.h>
		#include <linux/seq_file.h>

		static int dbg_show_requester_chan(struct seq_file s, void p)
		{
		int pos = 0;
		struct pxad_phy *phy = s->private;
		int i;
		u32 drcmr;

		pos += seq_printf(s, "DMA channel %d requester :\n", phy->idx);
		for (i = 0; i < 70; i++) {
		drcmr = readl_relaxed(phy->base + pxad_drcmr(i));
		if ((drcmr & DRCMR_CHLNUM) == phy->idx)
		pos += seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,
		!!(drcmr & DRCMR_MAPVLD));
		}
		return pos;
		}

		static inline int dbg_burst_from_dcmd(u32 dcmd)
		{
		int burst = (dcmd >> 16) & 0x3;

		return burst ? 4 << burst : 0;
		}

		static int is_phys_valid(unsigned long addr)
		{
		return pfn_valid(__phys_to_pfn(addr));
		}

		#define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "")
		#define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "")

		static int dbg_show_descriptors(struct seq_file s, void p)
		{
		struct pxad_phy *phy = s->private;
		int i, max_show = 20, burst, width;
		u32 dcmd;
		unsigned long phys_desc, ddadr;
		struct pxad_desc_hw *desc;

		phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR);

		seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);
		seq_printf(s, "[%03d] First descriptor unknown\n", 0);
		for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
		desc = phys_to_virt(phys_desc);
		dcmd = desc->dcmd;
		burst = dbg_burst_from_dcmd(dcmd);
		width = (1 << ((dcmd >> 14) & 0x3)) >> 1;

		seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
		i, phys_desc, desc);
		seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
		seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
		seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
		seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
		dcmd,
		PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
		PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
		PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
		PXA_DCMD_STR(ENDIAN), burst, width,
		dcmd & PXA_DCMD_LENGTH);
		phys_desc = desc->ddadr;
		}
		if (i == max_show)
		seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
		i, phys_desc);
		else
		seq_printf(s, "[%03d] Desc at %08lx is %s\n",
		i, phys_desc, phys_desc == DDADR_STOP ?
		"DDADR_STOP" : "invalid");

		return 0;
		}

		static int dbg_show_chan_state(struct seq_file s, void p)
		{
		struct pxad_phy *phy = s->private;
		u32 dcsr, dcmd;
		int burst, width;
		static const char * const str_prio[] = {
		"high", "normal", "low", "invalid"
		};

		dcsr = _phy_readl_relaxed(phy, DCSR);
		dcmd = _phy_readl_relaxed(phy, DCMD);
		burst = dbg_burst_from_dcmd(dcmd);
		width = (1 << ((dcmd >> 14) & 0x3)) >> 1;

		seq_printf(s, "DMA channel %d\n", phy->idx);
		seq_printf(s, "\tPriority : %s\n",
		str_prio[(phy->idx & 0xf) / 4]);
		seq_printf(s, "\tUnaligned transfer bit: %s\n",
		_phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
		"yes" : "no");
		seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
		dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
		PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),
		PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN),
		PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST),
		PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR),
		PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE),
		PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR),
		PXA_DCSR_STR(BUSERR));

		seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
		dcmd,
		PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
		PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
		PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
		PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH);
		seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR));
		seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR));
		seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR));

		return 0;
		}

		static int dbg_show_state(struct seq_file s, void p)
		{
		struct pxad_device *pdev = s->private;

		/* basic device status */
		seq_puts(s, "DMA engine status\n");
		seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);

		return 0;
		}

		#define DBGFS_FUNC_DECL(name) \
		static int dbg_open_##name(struct inode inode, struct file file) \
		{ \
		return single_open(file, dbg_show_##name, inode->i_private); \
		} \
		static const struct file_operations dbg_fops_##name = { \
		.owner = THIS_MODULE, \
		.open = dbg_open_##name, \
		.llseek = seq_lseek, \
		.read = seq_read, \
		.release = single_release, \
		}

		DBGFS_FUNC_DECL(state);
		DBGFS_FUNC_DECL(chan_state);
		DBGFS_FUNC_DECL(descriptors);
		DBGFS_FUNC_DECL(requester_chan);

		static struct dentry pxad_dbg_alloc_chan(struct pxad_device pdev,
		int ch, struct dentry *chandir)
		{
		char chan_name[11];
		struct dentry chan, chan_state = NULL, *chan_descr = NULL;
		struct dentry *chan_reqs = NULL;
		void *dt;

		scnprintf(chan_name, sizeof(chan_name), "%d", ch);
		chan = debugfs_create_dir(chan_name, chandir);
		dt = (void *)&pdev->phys[ch];

		if (chan)
		chan_state = debugfs_create_file("state", 0400, chan, dt,
		&dbg_fops_chan_state);
		if (chan_state)
		chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
		&dbg_fops_descriptors);
		if (chan_descr)
		chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
		&dbg_fops_requester_chan);
		if (!chan_reqs)
		goto err_state;

		return chan;

		err_state:
		debugfs_remove_recursive(chan);
		return NULL;
		}

		static void pxad_init_debugfs(struct pxad_device *pdev)
		{
		int i;
		struct dentry *chandir;

		pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);
		if (IS_ERR(pdev->dbgfs_root) \|\| !pdev->dbgfs_root)
		goto err_root;

		pdev->dbgfs_state = debugfs_create_file("state", 0400, pdev->dbgfs_root,
		pdev, &dbg_fops_state);
		if (!pdev->dbgfs_state)
		goto err_state;

		pdev->dbgfs_chan =
		kmalloc_array(pdev->nr_chans, sizeof(*pdev->dbgfs_state),
		GFP_KERNEL);
		if (!pdev->dbgfs_chan)
		goto err_alloc;

		chandir = debugfs_create_dir("channels", pdev->dbgfs_root);
		if (!chandir)
		goto err_chandir;

		for (i = 0; i < pdev->nr_chans; i++) {
		pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);
		if (!pdev->dbgfs_chan[i])
		goto err_chans;
		}

		return;
		err_chans:
		err_chandir:
		kfree(pdev->dbgfs_chan);
		err_alloc:
		err_state:
		debugfs_remove_recursive(pdev->dbgfs_root);
		err_root:
		pr_err("pxad: debugfs is not available\n");
		}

		static void pxad_cleanup_debugfs(struct pxad_device *pdev)
		{
		debugfs_remove_recursive(pdev->dbgfs_root);
		}
		#else
		static inline void pxad_init_debugfs(struct pxad_device *pdev) {}
		static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {}
		#endif

		static struct pxad_phy lookup_phy(struct pxad_chan pchan)
		{
		int prio, i;
		@@ -982,6 +1224,7 @@ static int pxad_remove(struct platform_device *op)
		{
		struct pxad_device *pdev = platform_get_drvdata(op);

		pxad_cleanup_debugfs(pdev);
		pxad_free_channels(&pdev->slave);
		dma_async_device_unregister(&pdev->slave);
		return 0;
		@@ -1154,6 +1397,7 @@ static int pxad_probe(struct platform_device *op)
		}

		platform_set_drvdata(op, pdev);
		pxad_init_debugfs(pdev);
		dev_info(pdev->slave.dev, "initialized %d channels\n", dma_channels);
		return 0;
		}

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