Commit c00054f5 authored Nov 13, 2017 by Bjorn Helgaas

PCI/ASPM: Use correct capability pointer to program LTR_L1.2_THRESHOLD



Previously we programmed the LTR_L1.2_THRESHOLD in the parent (upstream)
device using the capability pointer of the *child* (downstream) device,
which corrupted some random word of the parent's config space.

Use the parent's L1 SS capability pointer to program its
LTR_L1.2_THRESHOLD.

Fixes: aeda9ade ("PCI/ASPM: Configure L1 substate settings")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
CC: stable@vger.kernel.org	# v4.11+
CC: Rajat Jain <rajatja@google.com>

parent 94ac327e

drivers/pci/pcie/aspm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -657,7 +657,7 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
		0xFF00, link->l1ss.ctl1);

		/* Program LTR L1.2 threshold in both ports */
		pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1,
		pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
		0xE3FF0000, link->l1ss.ctl1);
		pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
		0xE3FF0000, link->l1ss.ctl1);

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