Commit bff70595 authored Aug 14, 2013 by Mark Rutland Committed by Catalin Marinas Mar 04, 2014

arm64: remove unnecessary cache flush at boot



Currently we flush the entire dcache at boot within __cpu_setup, but
this is unnecessary as the booting protocol demands that the dcache is
invalid and off upon entering the kernel. The presence of the cache
flush only serves to hide bugs in bootloaders, and is not safe in the
presence of SMP.

In an SMP boot scenario the CPUs enter coherency outside of the kernel,
and the primary CPU enables its caches before bringing up secondary
CPUs. Therefore if any secondary CPU has an entry in its cache (in
violation of the boot protocol), the primary CPU might snoop it even if
the secondary CPU's cache is disabled. The boot-time cache flush only
serves to hide a firmware bug, and slows down a cpu boot unnecessarily.

This patch removes the unnecessary boot-time cache flush.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
[catalin.marinas@arm.com: make __flush_dcache_all local only]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent addea9ef

arch/arm64/mm/cache.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -30,7 +30,7 @@
		*
		* Corrupted registers: x0-x7, x9-x11
		*/
		ENTRY(__flush_dcache_all)
		__flush_dcache_all:
		dsb sy // ensure ordering with previous memory accesses
		mrs x0, clidr_el1 // read clidr
		and x3, x0, #0x7000000 // extract loc from clidr

arch/arm64/mm/proc.S

+0 −6

Original line number	Diff line number	Diff line
		@@ -173,12 +173,6 @@ ENDPROC(cpu_do_switch_mm)
		* value of the SCTLR_EL1 register.
		*/
		ENTRY(__cpu_setup)
		/*
		* Preserve the link register across the function call.
		*/
		mov x28, lr
		bl __flush_dcache_all
		mov lr, x28
		ic iallu // I+BTB cache invalidate
		tlbi vmalle1is // invalidate I + D TLBs
		dsb sy

Admin message