Commit bfcf1ae2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/home/rmk/linux-2.6-arm 

* master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: 6126/1: ARM mpcore_wdt: fix build failure and other fixes
  ARM: 6125/1: ARM TWD: move TWD registers to common header
  ARM: 6110/1: Fix Thumb-2 kernel builds when UACCESS_WITH_MEMCPY is enabled
  ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP
  ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache ops
  ARM: 6106/1: Implement copy_to_user_page() for noMMU
  ARM: 6105/1: Fix the __arm_ioremap_caller() definition in nommu.c
parents ecbb458a 98af0570

arch/arm/include/asm/cacheflush.h

+4 −0
Original line number Diff line number Diff line
@@ -371,6 +371,10 @@ static inline void __flush_icache_all(void) 
#ifdef CONFIG_ARM_ERRATA_411920

	extern void v6_icache_inval_all(void);

	v6_icache_inval_all();

#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7

	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"

	    :

	    : "r" (0));

#else

	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"

	    :

arch/arm/include/asm/smp_twd.h

+17 −0
Original line number Diff line number Diff line 
#ifndef __ASMARM_SMP_TWD_H

#define __ASMARM_SMP_TWD_H



#define TWD_TIMER_LOAD			0x00

#define TWD_TIMER_COUNTER		0x04

#define TWD_TIMER_CONTROL		0x08

#define TWD_TIMER_INTSTAT		0x0C



#define TWD_WDOG_LOAD			0x20

#define TWD_WDOG_COUNTER		0x24

#define TWD_WDOG_CONTROL		0x28

#define TWD_WDOG_INTSTAT		0x2C

#define TWD_WDOG_RESETSTAT		0x30

#define TWD_WDOG_DISABLE		0x34



#define TWD_TIMER_CONTROL_ENABLE	(1 << 0)

#define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)

#define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)

#define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)



struct clock_event_device;



extern void __iomem *twd_base;

arch/arm/include/asm/tlbflush.h

+28 −1
Original line number Diff line number Diff line
@@ -46,6 +46,9 @@ 
#define TLB_V7_UIS_FULL (1 << 20)

#define TLB_V7_UIS_ASID (1 << 21)



/* Inner Shareable BTB operation (ARMv7 MP extensions) */

#define TLB_V7_IS_BTB	(1 << 22)



#define TLB_L2CLEAN_FR	(1 << 29)		/* Feroceon */

#define TLB_DCLEAN	(1 << 30)

#define TLB_WB		(1 << 31)
@@ -183,7 +186,7 @@ 
#endif



#ifdef CONFIG_SMP

#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \

#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \

			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)

#else

#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
@@ -339,6 +342,12 @@ static inline void local_flush_tlb_all(void) 
		dsb();

		isb();

	}

	if (tlb_flag(TLB_V7_IS_BTB)) {

		/* flush the branch target cache */

		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");

		dsb();

		isb();

	}

}



static inline void local_flush_tlb_mm(struct mm_struct *mm)
@@ -376,6 +385,12 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) 
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");

		dsb();

	}

	if (tlb_flag(TLB_V7_IS_BTB)) {

		/* flush the branch target cache */

		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");

		dsb();

		isb();

	}

}



static inline void
@@ -416,6 +431,12 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");

		dsb();

	}

	if (tlb_flag(TLB_V7_IS_BTB)) {

		/* flush the branch target cache */

		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");

		dsb();

		isb();

	}

}



static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
@@ -454,6 +475,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 
		dsb();

		isb();

	}

	if (tlb_flag(TLB_V7_IS_BTB)) {

		/* flush the branch target cache */

		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");

		dsb();

		isb();

	}

}



/*

arch/arm/kernel/smp_twd.c

+0 −17
Original line number Diff line number Diff line
@@ -21,23 +21,6 @@ 
#include <asm/smp_twd.h>

#include <asm/hardware/gic.h>



#define TWD_TIMER_LOAD 			0x00

#define TWD_TIMER_COUNTER		0x04

#define TWD_TIMER_CONTROL		0x08

#define TWD_TIMER_INTSTAT		0x0C



#define TWD_WDOG_LOAD			0x20

#define TWD_WDOG_COUNTER		0x24

#define TWD_WDOG_CONTROL		0x28

#define TWD_WDOG_INTSTAT		0x2C

#define TWD_WDOG_RESETSTAT		0x30

#define TWD_WDOG_DISABLE		0x34



#define TWD_TIMER_CONTROL_ENABLE	(1 << 0)

#define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)

#define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)

#define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)



/* set up by the platform code */

void __iomem *twd_base;

arch/arm/lib/clear_user.S

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ USER( strnebt r2, [r0]) 
		mov	r0, #0

		ldmfd	sp!, {r1, pc}

ENDPROC(__clear_user)

ENDPROC(__clear_user_std)



		.pushsection .fixup,"ax"

		.align	0

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