drm/i915: handle DDI-related assertions (bf507ef7) · Commits · 戴 / test

Prevent bogus asserts on DDI-related paths. Longer explanation from Eugeni by mail: "For the asserts there are 3 paths where we hit them: - in assert_fdi_tx (we don't have the FDI_TX_CTL anymore, backup plan DDI_FUNC_CTL is used instead) - in assert_fdi_tx_pll_enabled (we have the combination of iCLKIP and DDI_FUNC_CTL, plus PORT_CLK_SEL and PIPE_CLK_SEL now to make things work). We could use an assert here indeed - if we configure port to use one clock, and pipe to use another, everything hangs. Right now, we configure all of them in one place only; but yes, when DP code lands it will get more funky. - and in ironlake_fdi_pll_enable. I reuse part of this function (to configure the TU sizes), but as in the 1st case, FDI_TX_CTL is gone so I just ignore it here." Signed-off-by:

Eugeni Dodonov <eugeni.dodonov@intel.com> [danvet: Pasted Eugeni's explanation into the commit message.] Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_display.c

+25 −10

Original line number	Diff line number	Diff line
		@@ -953,9 +953,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
		u32 val;
		bool cur_state;

		if (IS_HASWELL(dev_priv->dev)) {
		/* On Haswell, DDI is used instead of FDI_TX_CTL */
		reg = DDI_FUNC_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
		} else {
		reg = FDI_TX_CTL(pipe);
		val = I915_READ(reg);
		cur_state = !!(val & FDI_TX_ENABLE);
		}
		WARN(cur_state != state,
		"FDI TX state assertion failure (expected %s, current %s)\n",
		state_string(state), state_string(cur_state));
		@@ -990,6 +997,10 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
		if (dev_priv->info->gen == 5)
		return;

		/* On Haswell, DDI ports are responsible for the FDI PLL setup */
		if (IS_HASWELL(dev_priv->dev))
		return;

		reg = FDI_TX_CTL(pipe);
		val = I915_READ(reg);
		WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
		@@ -2514,6 +2525,9 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
		POSTING_READ(reg);
		udelay(200);

		/* On Haswell, the PLL configuration for ports and pipes is handled
		* separately, as part of DDI setup */
		if (!IS_HASWELL(dev)) {
		/* Enable CPU FDI TX PLL, always on for Ironlake */
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		@@ -2524,6 +2538,7 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
		udelay(100);
		}
		}
		}

		static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
		{

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