Commit bf3e7628 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull mtd fixes from Miquel Raynal.

* 'mtd/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
  mtd: rawnand: stm32_fmc2: fix broken ECC
  mtd: spi-nor: Fix address width on flash chips > 16MB
  mtd: spi-nor: Don't copy self-pointing struct around
  mtd: rawnand: ifc: Move the ECC engine initialization to the right place
  mtd: rawnand: mxc: Move the ECC engine initialization to the right place
parents 44d80621 9efac6ce
Loading
Loading
Loading
Loading
+24 −19
Original line number Diff line number Diff line
@@ -707,6 +707,30 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)
{
	struct mtd_info *mtd = nand_to_mtd(chip);
	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
	struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
	u32 csor;

	csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);

	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
	if (csor & CSOR_NAND_ECC_DEC_EN) {
		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);

		/* Hardware generates ECC per 512 Bytes */
		chip->ecc.size = 512;
		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
			chip->ecc.bytes = 8;
			chip->ecc.strength = 4;
		} else {
			chip->ecc.bytes = 16;
			chip->ecc.strength = 8;
		}
	} else {
		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
	}

	dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
		nanddev_ntargets(&chip->base));
@@ -910,25 +934,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
		return -ENODEV;
	}

	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
	if (csor & CSOR_NAND_ECC_DEC_EN) {
		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);

		/* Hardware generates ECC per 512 Bytes */
		chip->ecc.size = 512;
		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
			chip->ecc.bytes = 8;
			chip->ecc.strength = 4;
		} else {
			chip->ecc.bytes = 16;
			chip->ecc.strength = 8;
		}
	} else {
		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
	}

	ret = fsl_ifc_sram_init(priv);
	if (ret)
		return ret;
+5 −12
Original line number Diff line number Diff line
@@ -1681,6 +1681,11 @@ static int mxcnd_attach_chip(struct nand_chip *chip)
	struct mxc_nand_host *host = nand_get_controller_data(chip);
	struct device *dev = mtd->dev.parent;

	chip->ecc.bytes = host->devtype_data->eccbytes;
	host->eccsize = host->devtype_data->eccsize;
	chip->ecc.size = 512;
	mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);

	switch (chip->ecc.engine_type) {
	case NAND_ECC_ENGINE_TYPE_ON_HOST:
		chip->ecc.read_page = mxc_nand_read_page;
@@ -1836,19 +1841,7 @@ static int mxcnd_probe(struct platform_device *pdev)
	if (host->devtype_data->axi_offset)
		host->regs_axi = host->base + host->devtype_data->axi_offset;

	this->ecc.bytes = host->devtype_data->eccbytes;
	host->eccsize = host->devtype_data->eccsize;

	this->legacy.select_chip = host->devtype_data->select_chip;
	this->ecc.size = 512;
	mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);

	if (host->pdata.hw_ecc) {
		this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
	} else {
		this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
		this->ecc.algo = NAND_ECC_ALGO_HAMMING;
	}

	/* NAND bus width determines access functions used by upper layer */
	if (host->pdata.width == 2)
+8 −7
Original line number Diff line number Diff line
@@ -1708,6 +1708,13 @@ static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
		return -EINVAL;
	}

	/* Default ECC settings in case they are not set in the device tree */
	if (!chip->ecc.size)
		chip->ecc.size = FMC2_ECC_STEP_SIZE;

	if (!chip->ecc.strength)
		chip->ecc.strength = FMC2_ECC_BCH8;

	ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
				   mtd->oobsize - FMC2_BBM_LEN);
	if (ret) {
@@ -1727,8 +1734,7 @@ static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)

	mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);

	if (chip->options & NAND_BUSWIDTH_16)
		stm32_fmc2_nfc_set_buswidth_16(nfc, true);
	stm32_fmc2_nfc_setup(chip);

	return 0;
}
@@ -1952,11 +1958,6 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
	chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
			 NAND_USES_DMA;

	/* Default ECC settings */
	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
	chip->ecc.size = FMC2_ECC_STEP_SIZE;
	chip->ecc.strength = FMC2_ECC_BCH8;

	/* Scan to find existence of the device */
	ret = nand_scan(chip, nand->ncs);
	if (ret)
+7 −6
Original line number Diff line number Diff line
@@ -2701,11 +2701,10 @@ static void spi_nor_sfdp_init_params(struct spi_nor *nor)

	memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));

	if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
	if (spi_nor_parse_sfdp(nor, nor->params)) {
		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
		nor->addr_width = 0;
		nor->flags &= ~SNOR_F_4B_OPCODES;
	} else {
		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
	}
}

@@ -3009,13 +3008,15 @@ static int spi_nor_set_addr_width(struct spi_nor *nor)
		/* already configured from SFDP */
	} else if (nor->info->addr_width) {
		nor->addr_width = nor->info->addr_width;
	} else if (nor->mtd.size > 0x1000000) {
		/* enable 4-byte addressing if the device exceeds 16MiB */
		nor->addr_width = 4;
	} else {
		nor->addr_width = 3;
	}

	if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) {
		/* enable 4-byte addressing if the device exceeds 16MiB */
		nor->addr_width = 4;
	}

	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
		dev_dbg(nor->dev, "address width is too large: %u\n",
			nor->addr_width);