Commit bf383fb6 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: convert nbio to use callbacks (v2) 



Cleans up and consolidates all of the per-asic logic.

v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming)

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 74e1d67c

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+43 −7
Original line number Diff line number Diff line
@@ -1428,16 +1428,52 @@ typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, u 
/*

 * amdgpu nbio functions

 *

 * Fix me :

 * 	Put more NBIO specifc func wraper here , for now just try to minimize the

 *	change to avoid use SOC15_REG_OFFSET in the constant array

 */

struct nbio_hdp_flush_reg {

	u32 ref_and_mask_cp0;

	u32 ref_and_mask_cp1;

	u32 ref_and_mask_cp2;

	u32 ref_and_mask_cp3;

	u32 ref_and_mask_cp4;

	u32 ref_and_mask_cp5;

	u32 ref_and_mask_cp6;

	u32 ref_and_mask_cp7;

	u32 ref_and_mask_cp8;

	u32 ref_and_mask_cp9;

	u32 ref_and_mask_sdma0;

	u32 ref_and_mask_sdma1;

};



struct amdgpu_nbio_funcs {

	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device*);

	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device*);

	u32 (*get_pcie_index_offset)(struct amdgpu_device*);

	u32 (*get_pcie_data_offset)(struct amdgpu_device*);

	const struct nbio_hdp_flush_reg *hdp_flush_reg;

	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);

	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);

	u32 (*get_rev_id)(struct amdgpu_device *adev);

	u32 (*get_atombios_scratch_regs)(struct amdgpu_device *adev, uint32_t idx);

	void (*set_atombios_scratch_regs)(struct amdgpu_device *adev,

					  uint32_t idx, uint32_t val);

	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);

	void (*hdp_flush)(struct amdgpu_device *adev);

	u32 (*get_memsize)(struct amdgpu_device *adev);

	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,

				    bool use_doorbell, int doorbell_index);

	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,

					 bool enable);

	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,

						  bool enable);

	void (*ih_doorbell_range)(struct amdgpu_device *adev,

				  bool use_doorbell, int doorbell_index);

	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,

						 bool enable);

	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,

						bool enable);

	void (*get_clockgating_state)(struct amdgpu_device *adev,

				      u32 *flags);

	void (*ih_control)(struct amdgpu_device *adev);

	void (*init_registers)(struct amdgpu_device *adev);

	void (*detect_hw_virt)(struct amdgpu_device *adev);

};

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −6
Original line number Diff line number Diff line
@@ -3552,12 +3552,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 
{

	struct amdgpu_device *adev = ring->adev;

	u32 ref_and_mask, reg_mem_engine;

	const struct nbio_hdp_flush_reg *nbio_hf_reg;



	if (ring->adev->flags & AMD_IS_APU)

		nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;

	else

		nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;

	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;



	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {

		switch (ring->me) {

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+3 −12
Original line number Diff line number Diff line
@@ -38,8 +38,6 @@ 
#include "soc15_common.h"

#include "umc/umc_6_0_sh_mask.h"



#include "nbio_v6_1.h"

#include "nbio_v7_0.h"

#include "gfxhub_v1_0.h"

#include "mmhub_v1_0.h"
@@ -332,10 +330,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 
	unsigned i, j;



	/* flush hdp cache */

	if (adev->flags & AMD_IS_APU)

		nbio_v7_0_hdp_flush(adev);

	else

		nbio_v6_1_hdp_flush(adev);

	adev->nbio_funcs->hdp_flush(adev);



	spin_lock(&adev->mc.invalidate_lock);
@@ -702,8 +697,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 


	/* size in MB on si */

	adev->mc.mc_vram_size =

		((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :

		 nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;

		adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;

	adev->mc.real_vram_size = adev->mc.mc_vram_size;



	if (!(adev->flags & AMD_IS_APU)) {
@@ -951,10 +945,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 
	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);



	/* After HDP is initialized, flush HDP.*/

	if (adev->flags & AMD_IS_APU)

		nbio_v7_0_hdp_flush(adev);

	else

		nbio_v6_1_hdp_flush(adev);

	adev->nbio_funcs->hdp_flush(adev);



	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)

		value = false;

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

+49 −32
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#define smnPCIE_CNTL2                                                                                   0x11180070

#define smnPCIE_CONFIG_CNTL                                                                             0x11180044



u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)

static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)

{

        u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -43,19 +43,19 @@ u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) 
	return tmp;

}



u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,

static u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,

					       uint32_t idx)

{

	return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);

}



void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,

static void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,

						uint32_t idx, uint32_t val)

{

	WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);

}



void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)

static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)

{

	if (enable)

		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
@@ -65,17 +65,17 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 
		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);

}



void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)

static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)

{

	WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);

}



u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)

static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)

{

	return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);

}



void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,

static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,

				  bool use_doorbell, int doorbell_index)

{

	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
@@ -93,13 +93,13 @@ void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 


}



void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,

static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,

					       bool enable)

{

	WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);

}



void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,

static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,

							bool enable)

{

	u32 tmp = 0;
@@ -119,7 +119,7 @@ void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 
}





void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,

static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,

					bool use_doorbell, int doorbell_index)

{

	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
@@ -133,7 +133,7 @@ void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, 
	WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);

}



void nbio_v6_1_ih_control(struct amdgpu_device *adev)

static void nbio_v6_1_ih_control(struct amdgpu_device *adev)

{

	u32 interrupt_cntl;
@@ -149,7 +149,7 @@ void nbio_v6_1_ih_control(struct amdgpu_device *adev) 
	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);

}



void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,

static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,

						       bool enable)

{

	uint32_t def, data;
@@ -177,7 +177,7 @@ void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
		WREG32_PCIE(smnCPM_CONTROL, data);

}



void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,

static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,

						      bool enable)

{

	uint32_t def, data;
@@ -197,7 +197,8 @@ void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
		WREG32_PCIE(smnPCIE_CNTL2, data);

}



void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)

static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,

					    u32 *flags)

{

	int data;
@@ -232,7 +233,7 @@ static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) 
	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);

}



const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {

static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {

	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,

	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,

	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
@@ -247,15 +248,7 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { 
	.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK

};



const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {

	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,

	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,

	.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,

	.get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,

};





void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)

static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)

{

	uint32_t reg;
@@ -272,7 +265,7 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) 
	}

}



void nbio_v6_1_init_registers(struct amdgpu_device *adev)

static void nbio_v6_1_init_registers(struct amdgpu_device *adev)

{

	uint32_t def, data;
@@ -283,3 +276,27 @@ void nbio_v6_1_init_registers(struct amdgpu_device *adev) 
	if (def != data)

		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);

}



const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {

	.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,

	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,

	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,

	.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,

	.get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,

	.get_rev_id = nbio_v6_1_get_rev_id,

	.get_atombios_scratch_regs = nbio_v6_1_get_atombios_scratch_regs,

	.set_atombios_scratch_regs = nbio_v6_1_set_atombios_scratch_regs,

	.mc_access_enable = nbio_v6_1_mc_access_enable,

	.hdp_flush = nbio_v6_1_hdp_flush,

	.get_memsize = nbio_v6_1_get_memsize,

	.sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,

	.enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,

	.enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,

	.ih_doorbell_range = nbio_v6_1_ih_doorbell_range,

	.update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,

	.update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,

	.get_clockgating_state = nbio_v6_1_get_clockgating_state,

	.ih_control = nbio_v6_1_ih_control,

	.init_registers = nbio_v6_1_init_registers,

	.detect_hw_virt = nbio_v6_1_detect_hw_virt,

};

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h

+0 −25
Original line number Diff line number Diff line
@@ -26,31 +26,6 @@ 


#include "soc15_common.h"



extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;

extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;



int nbio_v6_1_init(struct amdgpu_device *adev);

u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,

                                        uint32_t idx);

void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,

                                         uint32_t idx, uint32_t val);

void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable);

void nbio_v6_1_hdp_flush(struct amdgpu_device *adev);

u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev);

void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,

				  bool use_doorbell, int doorbell_index);

void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,

					bool enable);

void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,

					bool enable);

void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,

				bool use_doorbell, int doorbell_index);

void nbio_v6_1_ih_control(struct amdgpu_device *adev);

u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev);

void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable);

void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable);

void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);

void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev);

void nbio_v6_1_init_registers(struct amdgpu_device *adev);



#endif

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