KVM: X86: Fix MSR range of APIC registers in X2APIC mode (bf10bd0b) · Commits · 戴 / test

Only MSR address range 0x800 through 0x8ff is architecturally reserved and dedicated for accessing APIC registers in x2APIC mode. Fixes: ("KVM: x2apic interface to lapic") Signed-off-by:

Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20200616073307.16440-1-xiaoyao.li@intel.com> Cc: stable@vger.kernel.org Reviewed-by:

Sean Christopherson <sean.j.christopherson@intel.com> Reviewed-by:

Jim Mattson <jmattson@google.com> Signed-off-by:

Paolo Bonzini <pbonzini@redhat.com>

arch/x86/kvm/x86.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -2856,7 +2856,7 @@ int kvm_set_msr_common(struct kvm_vcpu vcpu, struct msr_data msr_info)
		return kvm_mtrr_set_msr(vcpu, msr, data);
		case MSR_IA32_APICBASE:
		return kvm_set_apic_base(vcpu, msr_info);
		case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
		case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
		return kvm_x2apic_msr_write(vcpu, msr, data);
		case MSR_IA32_TSCDEADLINE:
		kvm_set_lapic_tscdeadline_msr(vcpu, data);
		@@ -3196,7 +3196,7 @@ int kvm_get_msr_common(struct kvm_vcpu vcpu, struct msr_data msr_info)
		case MSR_IA32_APICBASE:
		msr_info->data = kvm_get_apic_base(vcpu);
		break;
		case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
		case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
		return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
		case MSR_IA32_TSCDEADLINE:
		msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);

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