Commit bef4a0ab authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux 

Pull clock framework changes from Michael Turquette:
 "The common clk framework changes for 3.12 are dominated by clock
  driver patches, both new drivers and fixes to existing.  A high
  percentage of these are for Samsung platforms like Exynos.  Core
  framework fixes and some new features like automagical clock
  re-parenting round out the patches"

* tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits)
  clk: only call get_parent if there is one
  clk: samsung: exynos5250: Simplify registration of PLL rate tables
  clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
  clk: samsung: exynos4: Register PLL rate tables for Exynos4210
  clk: samsung: exynos4: Reorder registration of mout_vpllsrc
  clk: samsung: pll: Add support for rate configuration of PLL46xx
  clk: samsung: pll: Use new registration method for PLL46xx
  clk: samsung: pll: Add support for rate configuration of PLL45xx
  clk: samsung: pll: Use new registration method for PLL45xx
  clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
  clk: samsung: exynos4: Remove checks for DT node
  clk: samsung: exynos4: Remove unused static clkdev aliases
  clk: samsung: Modify _get_rate() helper to use __clk_lookup()
  clk: samsung: exynos4: Use separate aliases for cpufreq related clocks
  clocksource: samsung_pwm_timer: Get clock from device tree
  ARM: dts: exynos4: Specify PWM clocks in PWM node
  pwm: samsung: Update DT bindings documentation to cover clocks
  clk: Move symbol export to proper location
  clk: fix new_parent dereference before null check
  clk: wm831x: Initialise wm831x pointer on init
  ...
parents 7eb69529 12d29886

Documentation/clk.txt

+26 −20
Original line number Diff line number Diff line
@@ -70,6 +70,10 @@ the operations defined in clk.h: 
						unsigned long parent_rate);

		long		(*round_rate)(struct clk_hw *hw, unsigned long,

						unsigned long *);

		long		(*determine_rate)(struct clk_hw *hw,

						unsigned long rate,

						unsigned long *best_parent_rate,

						struct clk **best_parent_clk);

		int		(*set_parent)(struct clk_hw *hw, u8 index);

		u8		(*get_parent)(struct clk_hw *hw);

		int		(*set_rate)(struct clk_hw *hw, unsigned long);
@@ -191,7 +195,8 @@ optional or must be evaluated on a case-by-case basis. 
.is_enabled     | y    |             |               |             |      |

                |      |             |               |             |      |

.recalc_rate    |      | y           |               |             |      |

.round_rate  |      | y           |               |             |      |

.round_rate     |      | y [1]       |               |             |      |

.determine_rate |      | y [1]       |               |             |      |

.set_rate       |      | y           |               |             |      |

                |      |             |               |             |      |

.set_parent     |      |             | n             | y           | n    |
@@ -199,6 +204,7 @@ optional or must be evaluated on a case-by-case basis. 
                |      |             |               |             |      |

.init           |      |             |               |             |      |

                -----------------------------------------------------------

[1] either one of round_rate or determine_rate is required.



Finally, register your clock at run-time with a hardware-specific

registration function.  This function simply populates struct clk_foo's

Documentation/devicetree/bindings/clock/exynos4-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable. 
  spi0_isp_sclk       380     Exynos4x12

  spi1_isp_sclk       381     Exynos4x12

  uart_isp_sclk       382     Exynos4x12

  tmu_apbif           383



		[Mux Clocks]

Documentation/devicetree/bindings/clock/exynos5250-clock.txt

+13 −1
Original line number Diff line number Diff line
@@ -59,6 +59,9 @@ clock which they consume. 
  sclk_spi0		154

  sclk_spi1		155

  sclk_spi2		156

  div_i2s1		157

  div_i2s2		158

  sclk_hdmiphy		159





   [Peripheral Clock Gates]
@@ -154,7 +157,16 @@ clock which they consume. 
  dsim0			341

  dp			342

  mixer			343

  hdmi			345

  hdmi			344

  g2d			345





   [Clock Muxes]



  Clock			ID

  ----------------------------

  mout_hdmi		1024





Example 1: An example of a clock controller node is listed below.

Documentation/devicetree/bindings/clock/exynos5420-clock.txt

+12 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ clock which they consume. 
  sclk_pwm		155

  sclk_gscl_wa		156

  sclk_gscl_wb		157

  sclk_hdmiphy		158



   [Peripheral Clock Gates]
@@ -179,6 +180,17 @@ clock which they consume. 
  fimc_lite3		495

  aclk_g3d		500

  g3d			501

  smmu_mixer		502



  Mux			ID

  ----------------------------



  mout_hdmi		640



  Divider		ID

  ----------------------------



  dout_pixel		768



Example 1: An example of a clock controller node is listed below.

Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt

0 → 100644
+77 −0
Original line number Diff line number Diff line 
* Samsung S3C64xx Clock Controller



The S3C64xx clock controller generates and supplies clock to various controllers

within the SoC. The clock binding described here is applicable to all SoCs in

the S3C64xx family.



Required Properties:



- compatible: should be one of the following.

  - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.

  - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.



- reg: physical base address of the controller and length of memory mapped

  region.



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. Some of the clocks are available only

on a particular S3C64xx SoC and this is specified where applicable.



All available clocks are defined as preprocessor macros in

dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device

tree sources.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "fin_pll" - PLL input clock (xtal/extclk) - required,

 - "xusbxti" - USB xtal - required,

 - "iiscdclk0" - I2S0 codec clock - optional,

 - "iiscdclk1" - I2S1 codec clock - optional,

 - "iiscdclk2" - I2S2 codec clock - optional,

 - "pcmcdclk0" - PCM0 codec clock - optional,

 - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.



Example: Clock controller node:



	clock: clock-controller@7e00f000 {

		compatible = "samsung,s3c6410-clock";

		reg = <0x7e00f000 0x1000>;

		#clock-cells = <1>;

	};



Example: Required external clocks:



	fin_pll: clock-fin-pll {

		compatible = "fixed-clock";

		clock-output-names = "fin_pll";

		clock-frequency = <12000000>;

		#clock-cells = <0>;

	};



	xusbxti: clock-xusbxti {

		compatible = "fixed-clock";

		clock-output-names = "xusbxti";

		clock-frequency = <48000000>;

		#clock-cells = <0>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller (refer to the standard clock bindings for information about

  "clocks" and "clock-names" properties):



		uart0: serial@7f005000 {

			compatible = "samsung,s3c6400-uart";

			reg = <0x7f005000 0x100>;

			interrupt-parent = <&vic1>;

			interrupts = <5>;

			clock-names = "uart", "clk_uart_baud2",

					"clk_uart_baud3";

			clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,

					<&clock SCLK_UART>;

			status = "disabled";

		};

CRA Git | Maintained and supported by SUSTech CRA and CCSE