Commit beecadea authored by Xi Wang's avatar Xi Wang Committed by James Bottomley
Browse files

[SCSI] mvsas: fix undefined bit shift



The macro bit(n) is defined as ((u32)1 << n), and thus it doesn't work
with n >= 32, such as in mvs_94xx_assign_reg_set():

	if (i >= 32) {
		mvi->sata_reg_set |= bit(i);
		...
	}

The shift ((u32)1 << n) with n >= 32 also leads to undefined behavior.
The result varies depending on the architecture.

This patch changes bit(n) to do a 64-bit shift.  It also simplifies
mv_ffc64() using __ffs64(), since invoking ffz() with ~0 is undefined.

Signed-off-by: default avatarXi Wang <xi.wang@gmail.com>
Acked-by: default avatarXiangliang Yu <yuxiangl@marvell.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 072f19b4
Loading
Loading
Loading
Loading
+2 −12
Original line number Diff line number Diff line
@@ -258,21 +258,11 @@ enum sas_sata_phy_regs {
#define SPI_ADDR_VLD_94XX         	(1U << 1)
#define SPI_CTRL_SpiStart_94XX     	(1U << 0)

#define mv_ffc(x)   ffz(x)

static inline int
mv_ffc64(u64 v)
{
	int i;
	i = mv_ffc((u32)v);
	if (i >= 0)
		return i;
	i = mv_ffc((u32)(v>>32));

	if (i != 0)
		return 32 + i;

	return -1;
	u64 x = ~v;
	return x ? __ffs64(x) : -1;
}

#define r_reg_set_enable(i) \
+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ extern struct kmem_cache *mvs_task_list_cache;
#define DEV_IS_EXPANDER(type)	\
	((type == EDGE_DEV) || (type == FANOUT_DEV))

#define bit(n) ((u32)1 << n)
#define bit(n) ((u64)1 << n)

#define for_each_phy(__lseq_mask, __mc, __lseq)			\
	for ((__mc) = (__lseq_mask), (__lseq) = 0;		\