Commit bea176fb authored by Oleksij Rempel's avatar Oleksij Rempel Committed by Thomas Bogendoerfer
Browse files

MIPS: reduce print level for cache information 



Default printk log level is KERN_WARNING. This makes automatic log
parsing problematic, since we get false positive alarms on not critical
information.

Set all not critical cache related information to KERN_INFO, the same level
as used on most kernel drivers.

Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent e5096625

arch/mips/mm/c-octeon.c

+9 −9
Original line number Diff line number Diff line
@@ -237,14 +237,14 @@ static void probe_octeon(void) 
	c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);



	if (smp_processor_id() == 0) {

		pr_notice("Primary instruction cache %ldkB, %s, %d way, "

		pr_info("Primary instruction cache %ldkB, %s, %d way, "

			"%d sets, linesize %d bytes.\n",

			icache_size >> 10,

			cpu_has_vtag_icache ?

				"virtually tagged" : "physically tagged",

			c->icache.ways, c->icache.sets, c->icache.linesz);



		pr_notice("Primary data cache %ldkB, %d-way, %d sets, "

		pr_info("Primary data cache %ldkB, %d-way, %d sets, "

			"linesize %d bytes.\n",

			dcache_size >> 10, c->dcache.ways,

			c->dcache.sets, c->dcache.linesz);

arch/mips/mm/c-r3k.c

+2 −2
Original line number Diff line number Diff line
@@ -316,9 +316,9 @@ void r3k_cache_init(void) 
	_dma_cache_wback = r3k_dma_cache_wback_inv;

	_dma_cache_inv = r3k_dma_cache_wback_inv;



	printk("Primary instruction cache %ldkB, linesize %ld bytes.\n",

	pr_info("Primary instruction cache %ldkB, linesize %ld bytes.\n",

		icache_size >> 10, icache_lsize);

	printk("Primary data cache %ldkB, linesize %ld bytes.\n",

	pr_info("Primary data cache %ldkB, linesize %ld bytes.\n",

		dcache_size >> 10, dcache_lsize);



	build_clear_page();

arch/mips/mm/c-r4k.c

+10 −10
Original line number Diff line number Diff line
@@ -1467,12 +1467,12 @@ static void probe_pcache(void) 
		c->icache.ways = 1;

	}



	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",

	pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",

		icache_size >> 10,

		c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",

		way_string[c->icache.ways], c->icache.linesz);



	printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",

	pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",

		dcache_size >> 10, way_string[c->dcache.ways],

		(c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",

		(c->dcache.flags & MIPS_CACHE_ALIASES) ?

arch/mips/mm/c-tx39.c

+2 −2
Original line number Diff line number Diff line
@@ -410,9 +410,9 @@ void tx39_cache_init(void) 
	current_cpu_data.icache.waybit = 0;

	current_cpu_data.dcache.waybit = 0;



	printk("Primary instruction cache %ldkB, linesize %d bytes\n",

	pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",

		icache_size >> 10, current_cpu_data.icache.linesz);

	printk("Primary data cache %ldkB, linesize %d bytes\n",

	pr_info("Primary data cache %ldkB, linesize %d bytes\n",

		dcache_size >> 10, current_cpu_data.dcache.linesz);



	build_clear_page();

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