Commit be61795b authored by Lubomir Rintel's avatar Lubomir Rintel Committed by Olof Johansson
Browse files

clk: mmp2: Add HSIC clocks 

There are two USB HSIC controllers on MMP2 and MMP3.

Link: https://lore.kernel.org/r/20191220065314.237624-3-lkundrak@v3.sk


Signed-off-by: default avatarLubomir Rintel <lkundrak@v3.sk>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 247aa9e4

drivers/clk/mmp/clk-of-mmp2.c

+6 −0
Original line number Diff line number Diff line
@@ -53,6 +53,8 @@ 
#define APMU_DISP1	0x110

#define APMU_CCIC0	0x50

#define APMU_CCIC1	0xf4

#define APMU_USBHSIC0	0xf8

#define APMU_USBHSIC1	0xfc

#define MPMU_UART_PLL	0x14



struct mmp2_clk_unit {
@@ -194,6 +196,8 @@ static struct mmp_clk_mix_config sdh_mix_config = { 
};



static DEFINE_SPINLOCK(usb_lock);

static DEFINE_SPINLOCK(usbhsic0_lock);

static DEFINE_SPINLOCK(usbhsic1_lock);



static DEFINE_SPINLOCK(disp0_lock);

static DEFINE_SPINLOCK(disp1_lock);
@@ -224,6 +228,8 @@ static struct mmp_param_div_clk apmu_div_clks[] = { 


static struct mmp_param_gate_clk apmu_gate_clks[] = {

	{MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},

	{MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock},

	{MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock},

	/* The gate clocks has mux parent. */

	{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},

	{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},

CRA Git | Maintained and supported by SUSTech CRA and CCSE