ARCv2: intc: Set default priority for all core interrupts (be568e78) · Commits · 戴 / test

After reset all interrupts in the core interrupt controller has the highest priority P0. If the platform supports Fast IRQs and has more than 1 banks of registers then CPU automatically switch banks of registers when P0 interrupt comes. The problem is that the kernel expects that by default switching of banks is not used by all interrupts. It is necessary to set a default nonzero priority for all available interrupts to avoid undefined behaviour. Signed-off-by:

Yuriy Kolerov <yuriy.kolerov@synopsys.com> Signed-off-by:

Vineet Gupta <vgupta@synopsys.com>

arch/arc/kernel/intc-arcv2.c

+11 −1

Original line number	Diff line number	Diff line
		@@ -32,7 +32,7 @@ struct bcr_irq_arcv2 {
		*/
		void arc_init_IRQ(void)
		{
		unsigned int tmp, irq_prio;
		unsigned int tmp, irq_prio, i;
		struct bcr_irq_arcv2 irq_bcr;

		struct aux_irq_ctrl {
		@@ -71,6 +71,16 @@ void arc_init_IRQ(void)
		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
		irq_bcr.firq ? " FIRQ (not used)":"");

		/*
		* Set a default priority for all available interrupts to prevent
		* switching of register banks if Fast IRQ and multiple register banks
		* are supported by CPU.
		*/
		for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
		write_aux_reg(AUX_IRQ_SELECT, i);
		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
		}

		/* setup status32, don't enable intr yet as kernel doesn't want */
		tmp = read_aux_reg(ARC_REG_STATUS32);
		tmp \|= STATUS_AD_MASK \| (ARCV2_IRQ_DEF_PRIO << 1);

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