MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines (be280764) · Commits · 戴 / test

Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache line can contain two instruction cache lines (64B), or four data cache lines (32B). Hardware prefetch Cache detects stream access, and prefetches ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr secondary cache module (ZSCM) on DMA from device so that data returned is coherent during DMA read operations. Signed-off-by:

Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-by:

Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:

Thomas Bogendoerfer <tsbogend@alpha.franken.de>

arch/mips/mm/c-r4k.c

+29 −0

Original line number	Diff line number	Diff line
		@@ -901,6 +901,31 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
		__sync();
		}

		static void prefetch_cache_inv(unsigned long addr, unsigned long size)
		{
		unsigned int linesz = cpu_scache_line_size();
		unsigned long addr0 = addr, addr1;

		addr0 &= ~(linesz - 1);
		addr1 = (addr0 + size - 1) & ~(linesz - 1);

		protected_writeback_scache_line(addr0);
		if (likely(addr1 != addr0))
		protected_writeback_scache_line(addr1);
		else
		return;

		addr0 += linesz;
		if (likely(addr1 != addr0))
		protected_writeback_scache_line(addr0);
		else
		return;

		addr1 -= linesz;
		if (likely(addr1 > addr0))
		protected_writeback_scache_line(addr0);
		}

		static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
		{
		/* Catch bad driver code */
		@@ -908,6 +933,10 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
		return;

		preempt_disable();

		if (current_cpu_type() == CPU_BMIPS5000)
		prefetch_cache_inv(addr, size);

		if (cpu_has_inclusive_pcaches) {
		if (size >= scache_size) {
		if (current_cpu_type() != CPU_LOONGSON64)

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