Commit be26667c authored by Arthur Kiyanovski's avatar Arthur Kiyanovski Committed by David S. Miller
Browse files

net: ena: fix indentations in ena_defs for better readability

parent 3a7b9d8d
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+133 −201
Original line number Diff line number Diff line
@@ -32,75 +32,49 @@
#ifndef _ENA_ADMIN_H_
#define _ENA_ADMIN_H_


enum ena_admin_aq_opcode {
	ENA_ADMIN_CREATE_SQ                         = 1,

	ENA_ADMIN_DESTROY_SQ                        = 2,

	ENA_ADMIN_CREATE_CQ                         = 3,

	ENA_ADMIN_DESTROY_CQ                        = 4,

	ENA_ADMIN_GET_FEATURE                       = 8,

	ENA_ADMIN_SET_FEATURE                       = 9,

	ENA_ADMIN_GET_STATS                         = 11,
};

enum ena_admin_aq_completion_status {
	ENA_ADMIN_SUCCESS                           = 0,

	ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,

	ENA_ADMIN_BAD_OPCODE                        = 2,

	ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,

	ENA_ADMIN_MALFORMED_REQUEST                 = 4,

	/* Additional status is provided in ACQ entry extended_status */
	ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,

	ENA_ADMIN_UNKNOWN_ERROR                     = 6,

	ENA_ADMIN_RESOURCE_BUSY                     = 7,
};

enum ena_admin_aq_feature_id {
	ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,

	ENA_ADMIN_MAX_QUEUES_NUM                    = 2,

	ENA_ADMIN_HW_HINTS                          = 3,

	ENA_ADMIN_LLQ                               = 4,

	ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,

	ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,

	ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG      = 12,

	ENA_ADMIN_MTU                               = 14,

	ENA_ADMIN_RSS_HASH_INPUT                    = 18,

	ENA_ADMIN_INTERRUPT_MODERATION              = 20,

	ENA_ADMIN_AENQ_CONFIG                       = 26,

	ENA_ADMIN_LINK_CONFIG                       = 27,

	ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,

	ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
};

enum ena_admin_placement_policy_type {
	/* descriptors and headers are in host memory */
	ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,

	/* descriptors and headers are in device memory (a.k.a Low Latency
	 * Queue)
	 */
@@ -109,38 +83,26 @@ enum ena_admin_placement_policy_type {

enum ena_admin_link_types {
	ENA_ADMIN_LINK_SPEED_1G                     = 0x1,

	ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,

	ENA_ADMIN_LINK_SPEED_5G                     = 0x4,

	ENA_ADMIN_LINK_SPEED_10G                    = 0x8,

	ENA_ADMIN_LINK_SPEED_25G                    = 0x10,

	ENA_ADMIN_LINK_SPEED_40G                    = 0x20,

	ENA_ADMIN_LINK_SPEED_50G                    = 0x40,

	ENA_ADMIN_LINK_SPEED_100G                   = 0x80,

	ENA_ADMIN_LINK_SPEED_200G                   = 0x100,

	ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
};

enum ena_admin_completion_policy_type {
	/* completion queue entry for each sq descriptor */
	ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,

	/* completion queue entry upon request in sq descriptor */
	ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,

	/* current queue head pointer is updated in OS memory upon sq
	 * descriptor request
	 */
	ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,

	/* current queue head pointer is updated in OS memory for each sq
	 * descriptor
	 */
@@ -153,13 +115,11 @@ enum ena_admin_completion_policy_type {
 */
enum ena_admin_get_stats_type {
	ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,

	ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
};

enum ena_admin_get_stats_scope {
	ENA_ADMIN_SPECIFIC_QUEUE                    = 0,

	ENA_ADMIN_ETH_TRAFFIC                       = 1,
};

@@ -231,7 +191,9 @@ struct ena_admin_acq_common_desc {

	u16 extended_status;

	/* serves as a hint what AQ entries can be revoked */
	/* indicates to the driver which AQ entry has been consumed by the
	 *    device and could be reused
	 */
	u16 sq_head_indx;
};

@@ -301,7 +263,6 @@ struct ena_admin_aq_create_sq_cmd {

enum ena_admin_sq_direction {
	ENA_ADMIN_SQ_DIRECTION_TX                   = 1,

	ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
};

@@ -665,7 +626,6 @@ struct ena_admin_feature_offload_desc {

enum ena_admin_hash_functions {
	ENA_ADMIN_TOEPLITZ                          = 1,

	ENA_ADMIN_CRC32                             = 2,
};

@@ -693,27 +653,17 @@ struct ena_admin_feature_rss_flow_hash_function {
/* RSS flow hash protocols */
enum ena_admin_flow_hash_proto {
	ENA_ADMIN_RSS_TCP4                          = 0,

	ENA_ADMIN_RSS_UDP4                          = 1,

	ENA_ADMIN_RSS_TCP6                          = 2,

	ENA_ADMIN_RSS_UDP6                          = 3,

	ENA_ADMIN_RSS_IP4                           = 4,

	ENA_ADMIN_RSS_IP6                           = 5,

	ENA_ADMIN_RSS_IP4_FRAG                      = 6,

	ENA_ADMIN_RSS_NOT_IP                        = 7,

	/* TCPv6 with extension header */
	ENA_ADMIN_RSS_TCP6_EX                       = 8,

	/* IPv6 with extension header */
	ENA_ADMIN_RSS_IP6_EX                        = 9,

	ENA_ADMIN_RSS_PROTO_NUM                     = 16,
};

@@ -721,19 +671,14 @@ enum ena_admin_flow_hash_proto {
enum ena_admin_flow_hash_fields {
	/* Ethernet Dest Addr */
	ENA_ADMIN_RSS_L2_DA                         = BIT(0),

	/* Ethernet Src Addr */
	ENA_ADMIN_RSS_L2_SA                         = BIT(1),

	/* ipv4/6 Dest Addr */
	ENA_ADMIN_RSS_L3_DA                         = BIT(2),

	/* ipv4/6 Src Addr */
	ENA_ADMIN_RSS_L3_SA                         = BIT(3),

	/* tcp/udp Dest Port */
	ENA_ADMIN_RSS_L4_DP                         = BIT(4),

	/* tcp/udp Src Port */
	ENA_ADMIN_RSS_L4_SP                         = BIT(5),
};
@@ -775,17 +720,11 @@ struct ena_admin_feature_rss_flow_hash_input {

enum ena_admin_os_type {
	ENA_ADMIN_OS_LINUX                          = 1,

	ENA_ADMIN_OS_WIN                            = 2,

	ENA_ADMIN_OS_DPDK                           = 3,

	ENA_ADMIN_OS_FREEBSD                        = 4,

	ENA_ADMIN_OS_IPXE                           = 5,

	ENA_ADMIN_OS_ESXI			    = 6,

	ENA_ADMIN_OS_GROUPS_NUM			    = 6,
};

@@ -982,23 +921,16 @@ struct ena_admin_aenq_common_desc {
/* asynchronous event notification groups */
enum ena_admin_aenq_group {
	ENA_ADMIN_LINK_CHANGE                       = 0,

	ENA_ADMIN_FATAL_ERROR                       = 1,

	ENA_ADMIN_WARNING                           = 2,

	ENA_ADMIN_NOTIFICATION                      = 3,

	ENA_ADMIN_KEEP_ALIVE                        = 4,

	ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
};

enum ena_admin_aenq_notification_syndrom {
	ENA_ADMIN_SUSPEND                           = 0,

	ENA_ADMIN_RESUME                            = 1,

	ENA_ADMIN_UPDATE_HINTS                      = 2,
};

+108 −115
Original line number Diff line number Diff line
@@ -34,23 +34,16 @@

enum ena_eth_io_l3_proto_index {
	ENA_ETH_IO_L3_PROTO_UNKNOWN                 = 0,

	ENA_ETH_IO_L3_PROTO_IPV4                    = 8,

	ENA_ETH_IO_L3_PROTO_IPV6                    = 11,

	ENA_ETH_IO_L3_PROTO_FCOE                    = 21,

	ENA_ETH_IO_L3_PROTO_ROCE                    = 22,
};

enum ena_eth_io_l4_proto_index {
	ENA_ETH_IO_L4_PROTO_UNKNOWN                 = 0,

	ENA_ETH_IO_L4_PROTO_TCP                     = 12,

	ENA_ETH_IO_L4_PROTO_UDP                     = 13,

	ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE          = 23,
};

+97 −109
Original line number Diff line number Diff line
@@ -34,37 +34,25 @@

enum ena_regs_reset_reason_types {
	ENA_REGS_RESET_NORMAL                       = 0,

	ENA_REGS_RESET_KEEP_ALIVE_TO                = 1,

	ENA_REGS_RESET_ADMIN_TO                     = 2,

	ENA_REGS_RESET_MISS_TX_CMPL                 = 3,

	ENA_REGS_RESET_INV_RX_REQ_ID                = 4,

	ENA_REGS_RESET_INV_TX_REQ_ID                = 5,

	ENA_REGS_RESET_TOO_MANY_RX_DESCS            = 6,

	ENA_REGS_RESET_INIT_ERR                     = 7,

	ENA_REGS_RESET_DRIVER_INVALID_STATE         = 8,

	ENA_REGS_RESET_OS_TRIGGER                   = 9,

	ENA_REGS_RESET_OS_NETDEV_WD                 = 10,

	ENA_REGS_RESET_SHUTDOWN                     = 11,

	ENA_REGS_RESET_USER_TRIGGER                 = 12,

	ENA_REGS_RESET_GENERIC                      = 13,

	ENA_REGS_RESET_MISS_INTERRUPT               = 14,
};

/* ena_registers offsets */

/* 0 base */
#define ENA_REGS_VERSION_OFF                                0x0
#define ENA_REGS_CONTROLLER_VERSION_OFF                     0x4
#define ENA_REGS_CAPS_OFF                                   0x8