Commit bdcf11de authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-5.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:

 - A fix for a lockdep issue to avoid an asserting triggering during
   early boot. There shouldn't be any incorrect behavior as the system
   isn't concurrent at the time.

 - The addition of a missing fence when installing early fixmap
   mappings.

 - A corretion to the K210 device tree's interrupt map.

 - A fix for M-mode timer handling on the K210.

* tag 'riscv-for-linus-5.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  RISC-V: Resurrect the MMIO timer implementation for M-mode systems
  riscv: Fix Kendryte K210 device tree
  riscv: Add sfence.vma after early page table changes
  RISC-V: Take text_mutex in ftrace_init_nop()
parents d0373c14 d5be89a8

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ config RISCV 
	select ARCH_WANT_FRAME_POINTERS

	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT

	select CLONE_BACKWARDS

	select CLINT_TIMER if !MMU

	select COMMON_CLK

	select EDAC_SUPPORT

	select GENERIC_ARCH_TOPOLOGY if SMP

arch/riscv/boot/dts/kendryte/k210.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -95,10 +95,12 @@ 
			#clock-cells = <1>;

		};



		clint0: interrupt-controller@2000000 {

		clint0: clint@2000000 {

			#interrupt-cells = <1>;

			compatible = "riscv,clint0";

			reg = <0x2000000 0xC000>;

			interrupts-extended = <&cpu0_intc 3>,  <&cpu1_intc 3>;

			interrupts-extended =  <&cpu0_intc 3 &cpu0_intc 7

						&cpu1_intc 3 &cpu1_intc 7>;

			clocks = <&sysctl K210_CLK_ACLK>;

		};

arch/riscv/include/asm/clint.h

0 → 100644
+26 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2020 Google, Inc

 */



#ifndef _ASM_RISCV_CLINT_H

#define _ASM_RISCV_CLINT_H



#include <linux/types.h>

#include <asm/mmio.h>



#ifdef CONFIG_RISCV_M_MODE

/*

 * This lives in the CLINT driver, but is accessed directly by timex.h to avoid

 * any overhead when accessing the MMIO timer.

 *

 * The ISA defines mtime as a 64-bit memory-mapped register that increments at

 * a constant frequency, but it doesn't define some other constraints we depend

 * on (most notably ordering constraints, but also some simpler stuff like the

 * memory layout).  Thus, this is called "clint_time_val" instead of something

 * like "riscv_mtime", to signify that these non-ISA assumptions must hold.

 */

extern u64 __iomem *clint_time_val;

#endif



#endif

arch/riscv/include/asm/ftrace.h

+7 −0
Original line number Diff line number Diff line
@@ -66,6 +66,13 @@ do { \ 
 * Let auipc+jalr be the basic *mcount unit*, so we make it 8 bytes here.

 */

#define MCOUNT_INSN_SIZE 8



#ifndef __ASSEMBLY__

struct dyn_ftrace;

int ftrace_init_nop(struct module *mod, struct dyn_ftrace *rec);

#define ftrace_init_nop ftrace_init_nop

#endif



#endif



#endif /* _ASM_RISCV_FTRACE_H */

arch/riscv/include/asm/timex.h

+27 −0
Original line number Diff line number Diff line
@@ -10,6 +10,31 @@ 


typedef unsigned long cycles_t;



#ifdef CONFIG_RISCV_M_MODE



#include <asm/clint.h>



#ifdef CONFIG_64BIT

static inline cycles_t get_cycles(void)

{

	return readq_relaxed(clint_time_val);

}

#else /* !CONFIG_64BIT */

static inline u32 get_cycles(void)

{

	return readl_relaxed(((u32 *)clint_time_val));

}

#define get_cycles get_cycles



static inline u32 get_cycles_hi(void)

{

	return readl_relaxed(((u32 *)clint_time_val) + 1);

}

#define get_cycles_hi get_cycles_hi

#endif /* CONFIG_64BIT */



#else /* CONFIG_RISCV_M_MODE */



static inline cycles_t get_cycles(void)

{

	return csr_read(CSR_TIME);
@@ -41,6 +66,8 @@ static inline u64 get_cycles64(void) 
}

#endif /* CONFIG_64BIT */



#endif /* !CONFIG_RISCV_M_MODE */



#define ARCH_HAS_READ_CURRENT_TIMER

static inline int read_current_timer(unsigned long *timer_val)

{

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