Commit bdc7c970 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'topic/ppc-kvm' into next 

Merge our topic branch shared with KVM. In particular this includes the
rewrite of the idle code into C.
parents 7ae3f6e1 e9cef018

Documentation/powerpc/DAWR-POWER9.txt

+32 −0
Original line number Diff line number Diff line
@@ -56,3 +56,35 @@ POWER9. Loads and stores to the watchpoint locations will not be 
trapped in GDB. The watchpoint is remembered, so if the guest is

migrated back to the POWER8 host, it will start working again.



Force enabling the DAWR

=============================

Kernels (since ~v5.2) have an option to force enable the DAWR via:



  echo Y > /sys/kernel/debug/powerpc/dawr_enable_dangerous



This enables the DAWR even on POWER9.



This is a dangerous setting, USE AT YOUR OWN RISK.



Some users may not care about a bad user crashing their box

(ie. single user/desktop systems) and really want the DAWR.  This

allows them to force enable DAWR.



This flag can also be used to disable DAWR access. Once this is

cleared, all DAWR access should be cleared immediately and your

machine once again safe from crashing.



Userspace may get confused by toggling this. If DAWR is force

enabled/disabled between getting the number of breakpoints (via

PTRACE_GETHWDBGINFO) and setting the breakpoint, userspace will get an

inconsistent view of what's available. Similarly for guests.



For the DAWR to be enabled in a KVM guest, the DAWR needs to be force

enabled in the host AND the guest. For this reason, this won't work on

POWERVM as it doesn't allow the HCALL to work. Writes of 'Y' to the

dawr_enable_dangerous file will fail if the hypervisor doesn't support

writing the DAWR.



To double check the DAWR is working, run this kernel selftest:

  tools/testing/selftests/powerpc/ptrace/ptrace-hwbreak.c

Any errors/failures/skips mean something is wrong.

arch/powerpc/include/asm/cpuidle.h

+3 −16
Original line number Diff line number Diff line
@@ -27,10 +27,11 @@ 
 * the THREAD_WINKLE_BITS are set, which indicate which threads have not

 * yet woken from the winkle state.

 */

#define PNV_CORE_IDLE_LOCK_BIT			0x10000000

#define NR_PNV_CORE_IDLE_LOCK_BIT		28

#define PNV_CORE_IDLE_LOCK_BIT			(1ULL << NR_PNV_CORE_IDLE_LOCK_BIT)



#define PNV_CORE_IDLE_WINKLE_COUNT_SHIFT	16

#define PNV_CORE_IDLE_WINKLE_COUNT		0x00010000

#define PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT	0x00080000

#define PNV_CORE_IDLE_WINKLE_COUNT_BITS		0x000F0000

#define PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT	8

#define PNV_CORE_IDLE_THREAD_WINKLE_BITS	0x0000FF00
@@ -68,16 +69,6 @@ 
#define ERR_DEEP_STATE_ESL_MISMATCH	-2



#ifndef __ASSEMBLY__

/* Additional SPRs that need to be saved/restored during stop */

struct stop_sprs {

	u64 pid;

	u64 ldbar;

	u64 fscr;

	u64 hfscr;

	u64 mmcr1;

	u64 mmcr2;

	u64 mmcra;

};



#define PNV_IDLE_NAME_LEN    16

struct pnv_idle_states_t {
@@ -92,10 +83,6 @@ struct pnv_idle_states_t { 


extern struct pnv_idle_states_t *pnv_idle_states;

extern int nr_pnv_idle_states;

extern u32 pnv_fastsleep_workaround_at_entry[];

extern u32 pnv_fastsleep_workaround_at_exit[];



extern u64 pnv_first_deep_stop_state;



unsigned long pnv_cpu_offline(unsigned int cpu);

int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags);

arch/powerpc/include/asm/hw_breakpoint.h

+8 −0
Original line number Diff line number Diff line
@@ -90,10 +90,18 @@ static inline void hw_breakpoint_disable(void) 
extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);

int hw_breakpoint_handler(struct die_args *args);



extern int set_dawr(struct arch_hw_breakpoint *brk);

extern bool dawr_force_enable;

static inline bool dawr_enabled(void)

{

	return dawr_force_enable;

}



#else	/* CONFIG_HAVE_HW_BREAKPOINT */

static inline void hw_breakpoint_disable(void) { }

static inline void thread_change_pc(struct task_struct *tsk,

					struct pt_regs *regs) { }

static inline bool dawr_enabled(void) { return false; }

#endif	/* CONFIG_HAVE_HW_BREAKPOINT */

#endif	/* __KERNEL__ */

#endif	/* _PPC_BOOK3S_64_HW_BREAKPOINT_H */

arch/powerpc/include/asm/opal-api.h

+4 −3
Original line number Diff line number Diff line
@@ -186,8 +186,8 @@ 
#define OPAL_XIVE_FREE_IRQ			140

#define OPAL_XIVE_SYNC				141

#define OPAL_XIVE_DUMP				142

#define OPAL_XIVE_RESERVED3			143

#define OPAL_XIVE_RESERVED4			144

#define OPAL_XIVE_GET_QUEUE_STATE		143

#define OPAL_XIVE_SET_QUEUE_STATE		144

#define OPAL_SIGNAL_SYSTEM_RESET		145

#define OPAL_NPU_INIT_CONTEXT			146

#define OPAL_NPU_DESTROY_CONTEXT		147
@@ -210,7 +210,8 @@ 
#define OPAL_PCI_GET_PBCQ_TUNNEL_BAR		164

#define OPAL_PCI_SET_PBCQ_TUNNEL_BAR		165

#define	OPAL_NX_COPROC_INIT			167

#define OPAL_LAST				167

#define OPAL_XIVE_GET_VP_STATE			170

#define OPAL_LAST				170



#define QUIESCE_HOLD			1 /* Spin all calls at entry */

#define QUIESCE_REJECT			2 /* Fail all calls with OPAL_BUSY */

arch/powerpc/include/asm/opal.h

+7 −0
Original line number Diff line number Diff line
@@ -279,6 +279,13 @@ int64_t opal_xive_allocate_irq(uint32_t chip_id); 
int64_t opal_xive_free_irq(uint32_t girq);

int64_t opal_xive_sync(uint32_t type, uint32_t id);

int64_t opal_xive_dump(uint32_t type, uint32_t id);

int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,

				  __be32 *out_qtoggle,

				  __be32 *out_qindex);

int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,

				  uint32_t qtoggle,

				  uint32_t qindex);

int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);

int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,

			uint64_t desc, uint16_t pe_number);

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