Commit bdb50274 authored by Emily Deng's avatar Emily Deng Committed by Alex Deucher
Browse files

drm/amdgpu/sriov: Correct some register program method 



For the VF, some registers only could be programmed with RLC.

Signed-off-by: default avatarEmily Deng <Emily.Deng@amd.com>
Reviewed-by: default avatarTrigger Huang <Trigger.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 443e902e

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+5 −5
Original line number Diff line number Diff line
@@ -1927,17 +1927,17 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 
		if (i == 0) {

			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);

			WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);

			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);

			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);

			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);

		} else {

			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);

			WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);

			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);

			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

				(adev->gmc.private_aperture_start >> 48));

			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

				(adev->gmc.shared_aperture_start >> 48));

			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);

			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);

		}

	}

	soc15_grbm_select(adev, 0, 0, 0, 0);
@@ -3046,7 +3046,7 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 
					(adev->doorbell_index.userqueue_end * 2) << 2);

	}



	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

	       mqd->cp_hqd_pq_doorbell_control);



	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+4 −4
Original line number Diff line number Diff line
@@ -146,12 +146,12 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);

	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);



	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);

	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);



	tmp = mmVM_L2_CNTL3_DEFAULT;

	if (adev->gmc.translate_further) {
@@ -163,12 +163,12 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

	}

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);

	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);



	tmp = mmVM_L2_CNTL4_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);

	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);

}



static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)

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