Commit bdb2c52a authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding
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ARM: tegra: Update sound node clocks in device tree



clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block but were
previously erroneously provided by the clock and reset controller.

clk_out_1 is dedicated for audio mclk on Tegra30 through Tegra210.

This patch updates device tree sound node to use clk_out_1 from the PMC
provider as mclk and uses assigned-clock properties to specify clock
parents for clk_out_1 and extern1.

Tested-by: default avatarDmitry Osipenko <digetx@gmail.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 86614b5d
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+7 −1
Original line number Diff line number Diff line
@@ -1296,7 +1296,13 @@

		clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
			 <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA114_CLK_EXTERN1>;
			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";

		assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;

		assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
					 <&tegra_car TEGRA114_CLK_EXTERN1>;
	};
};
+7 −1
Original line number Diff line number Diff line
@@ -2009,8 +2009,14 @@
		nvidia,audio-codec = <&sgtl5000>;
		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA124_CLK_EXTERN1>;
			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";

		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;

		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
					 <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	thermal-zones {
+7 −1
Original line number Diff line number Diff line
@@ -2001,8 +2001,14 @@
		nvidia,audio-codec = <&sgtl5000>;
		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA124_CLK_EXTERN1>;
			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";

		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;

		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
					 <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	thermal-zones {
+7 −1
Original line number Diff line number Diff line
@@ -2052,8 +2052,14 @@

		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA124_CLK_EXTERN1>;
			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";

		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;

		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
					 <&tegra_car TEGRA124_CLK_EXTERN1>;
	};

	thermal-zones {
+7 −1
Original line number Diff line number Diff line
@@ -788,9 +788,15 @@

		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA124_CLK_EXTERN1>;
			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";

		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;

		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
					 <&tegra_car TEGRA124_CLK_EXTERN1>;

		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
		nvidia,mic-det-gpios =
				<&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
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