Merge tag 'tegra-for-3.9-soc-ccf' of... (bda6f8e6) · Commits · 戴 / test

Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt

0 → 100644

+205 −0

Original line number	Diff line number	Diff line
		NVIDIA Tegra20 Clock And Reset Controller

		This binding uses the common clock binding:
		Documentation/devicetree/bindings/clock/clock-bindings.txt

		The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
		for muxing and gating Tegra's clocks, and setting their rates.

		Required properties :
		- compatible : Should be "nvidia,tegra20-car"
		- reg : Should contain CAR registers location and length
		- clocks : Should contain phandle and clock specifiers for two clocks:
		the 32 KHz "32k_in", and the board-specific oscillator "osc".
		- #clock-cells : Should be 1.
		In clock consumers, this cell represents the clock ID exposed by the CAR.

		The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
		registers. These IDs often match those in the CAR's RST_DEVICES registers,
		but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
		this case, those clocks are assigned IDs above 95 in order to highlight
		this issue. Implementations that interpret these clock IDs as bit values
		within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
		explicitly handle these special cases.

		The balance of the clocks controlled by the CAR are assigned IDs of 96 and
		above.

		0 cpu
		1 unassigned
		2 unassigned
		3 ac97
		4 rtc
		5 tmr
		6 uart1
		7 unassigned (register bit affects uart2 and vfir)
		8 gpio
		9 sdmmc2
		10 unassigned (register bit affects spdif_in and spdif_out)
		11 i2s1
		12 i2c1
		13 ndflash
		14 sdmmc1
		15 sdmmc4
		16 twc
		17 pwm
		18 i2s2
		19 epp
		20 unassigned (register bit affects vi and vi_sensor)
		21 2d
		22 usbd
		23 isp
		24 3d
		25 ide
		26 disp2
		27 disp1
		28 host1x
		29 vcp
		30 unassigned
		31 cache2

		32 mem
		33 ahbdma
		34 apbdma
		35 unassigned
		36 kbc
		37 stat_mon
		38 pmc
		39 fuse
		40 kfuse
		41 sbc1
		42 snor
		43 spi1
		44 sbc2
		45 xio
		46 sbc3
		47 dvc
		48 dsi
		49 unassigned (register bit affects tvo and cve)
		50 mipi
		51 hdmi
		52 csi
		53 tvdac
		54 i2c2
		55 uart3
		56 unassigned
		57 emc
		58 usb2
		59 usb3
		60 mpe
		61 vde
		62 bsea
		63 bsev

		64 speedo
		65 uart4
		66 uart5
		67 i2c3
		68 sbc4
		69 sdmmc3
		70 pcie
		71 owr
		72 afi
		73 csite
		74 unassigned
		75 avpucq
		76 la
		77 unassigned
		78 unassigned
		79 unassigned
		80 unassigned
		81 unassigned
		82 unassigned
		83 unassigned
		84 irama
		85 iramb
		86 iramc
		87 iramd
		88 cram2
		89 audio_2x a/k/a audio_2x_sync_clk
		90 clk_d
		91 unassigned
		92 sus
		93 cdev1
		94 cdev2
		95 unassigned

		96 uart2
		97 vfir
		98 spdif_in
		99 spdif_out
		100 vi
		101 vi_sensor
		102 tvo
		103 cve
		104 osc
		105 clk_32k a/k/a clk_s
		106 clk_m
		107 sclk
		108 cclk
		109 hclk
		110 pclk
		111 blink
		112 pll_a
		113 pll_a_out0
		114 pll_c
		115 pll_c_out1
		116 pll_d
		117 pll_d_out0
		118 pll_e
		119 pll_m
		120 pll_m_out1
		121 pll_p
		122 pll_p_out1
		123 pll_p_out2
		124 pll_p_out3
		125 pll_p_out4
		126 pll_s
		127 pll_u
		128 pll_x
		129 cop a/k/a avp
		130 audio a/k/a audio_sync_clk
		131 pll_ref
		132 twd

		Example SoC include file:

		/ {
		tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
		};

		usb@c5004000 {
		clocks = <&tegra_car 58>; /* usb2 */
		};
		};

		Example board file:

		/ {
		clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		osc: clock@0 {
		compatible = "fixed-clock";
		reg = <0>;
		#clock-cells = <0>;
		clock-frequency = <12000000>;
		};

		clk_32k: clock@1 {
		compatible = "fixed-clock";
		reg = <1>;
		#clock-cells = <0>;
		clock-frequency = <32768>;
		};
		};

		&tegra_car {
		clocks = <&clk_32k> <&osc>;
		};
		};

Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt

0 → 100644

+262 −0

Original line number	Diff line number	Diff line
		NVIDIA Tegra30 Clock And Reset Controller

		This binding uses the common clock binding:
		Documentation/devicetree/bindings/clock/clock-bindings.txt

		The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
		for muxing and gating Tegra's clocks, and setting their rates.

		Required properties :
		- compatible : Should be "nvidia,tegra30-car"
		- reg : Should contain CAR registers location and length
		- clocks : Should contain phandle and clock specifiers for two clocks:
		the 32 KHz "32k_in", and the board-specific oscillator "osc".
		- #clock-cells : Should be 1.
		In clock consumers, this cell represents the clock ID exposed by the CAR.

		The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
		registers. These IDs often match those in the CAR's RST_DEVICES registers,
		but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
		this case, those clocks are assigned IDs above 160 in order to highlight
		this issue. Implementations that interpret these clock IDs as bit values
		within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
		explicitly handle these special cases.

		The balance of the clocks controlled by the CAR are assigned IDs of 160 and
		above.

		0 cpu
		1 unassigned
		2 unassigned
		3 unassigned
		4 rtc
		5 timer
		6 uarta
		7 unassigned (register bit affects uartb and vfir)
		8 gpio
		9 sdmmc2
		10 unassigned (register bit affects spdif_in and spdif_out)
		11 i2s1
		12 i2c1
		13 ndflash
		14 sdmmc1
		15 sdmmc4
		16 unassigned
		17 pwm
		18 i2s2
		19 epp
		20 unassigned (register bit affects vi and vi_sensor)
		21 2d
		22 usbd
		23 isp
		24 3d
		25 unassigned
		26 disp2
		27 disp1
		28 host1x
		29 vcp
		30 i2s0
		31 cop_cache

		32 mc
		33 ahbdma
		34 apbdma
		35 unassigned
		36 kbc
		37 statmon
		38 pmc
		39 unassigned (register bit affects fuse and fuse_burn)
		40 kfuse
		41 sbc1
		42 nor
		43 unassigned
		44 sbc2
		45 unassigned
		46 sbc3
		47 i2c5
		48 dsia
		49 unassigned (register bit affects cve and tvo)
		50 mipi
		51 hdmi
		52 csi
		53 tvdac
		54 i2c2
		55 uartc
		56 unassigned
		57 emc
		58 usb2
		59 usb3
		60 mpe
		61 vde
		62 bsea
		63 bsev

		64 speedo
		65 uartd
		66 uarte
		67 i2c3
		68 sbc4
		69 sdmmc3
		70 pcie
		71 owr
		72 afi
		73 csite
		74 pciex
		75 avpucq
		76 la
		77 unassigned
		78 unassigned
		79 dtv
		80 ndspeed
		81 i2cslow
		82 dsib
		83 unassigned
		84 irama
		85 iramb
		86 iramc
		87 iramd
		88 cram2
		89 unassigned
		90 audio_2x a/k/a audio_2x_sync_clk
		91 unassigned
		92 csus
		93 cdev2
		94 cdev1
		95 unassigned

		96 cpu_g
		97 cpu_lp
		98 3d2
		99 mselect
		100 tsensor
		101 i2s3
		102 i2s4
		103 i2c4
		104 sbc5
		105 sbc6
		106 d_audio
		107 apbif
		108 dam0
		109 dam1
		110 dam2
		111 hda2codec_2x
		112 atomics
		113 audio0_2x
		114 audio1_2x
		115 audio2_2x
		116 audio3_2x
		117 audio4_2x
		118 audio5_2x
		119 actmon
		120 extern1
		121 extern2
		122 extern3
		123 sata_oob
		124 sata
		125 hda
		127 se
		128 hda2hdmi
		129 sata_cold

		160 uartb
		161 vfir
		162 spdif_in
		163 spdif_out
		164 vi
		165 vi_sensor
		166 fuse
		167 fuse_burn
		168 cve
		169 tvo

		170 clk_32k
		171 clk_m
		172 clk_m_div2
		173 clk_m_div4
		174 pll_ref
		175 pll_c
		176 pll_c_out1
		177 pll_m
		178 pll_m_out1
		179 pll_p
		180 pll_p_out1
		181 pll_p_out2
		182 pll_p_out3
		183 pll_p_out4
		184 pll_a
		185 pll_a_out0
		186 pll_d
		187 pll_d_out0
		188 pll_d2
		189 pll_d2_out0
		190 pll_u
		191 pll_x
		192 pll_x_out0
		193 pll_e
		194 spdif_in_sync
		195 i2s0_sync
		196 i2s1_sync
		197 i2s2_sync
		198 i2s3_sync
		199 i2s4_sync
		200 vimclk
		201 audio0
		202 audio1
		203 audio2
		204 audio3
		205 audio4
		206 audio5
		207 clk_out_1 (extern1)
		208 clk_out_2 (extern2)
		209 clk_out_3 (extern3)
		210 sclk
		211 blink
		212 cclk_g
		213 cclk_lp
		214 twd
		215 cml0
		216 cml1
		217 hclk
		218 pclk

		Example SoC include file:

		/ {
		tegra_car: clock {
		compatible = "nvidia,tegra30-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
		};

		usb@c5004000 {
		clocks = <&tegra_car 58>; /* usb2 */
		};
		};

		Example board file:

		/ {
		clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		osc: clock@0 {
		compatible = "fixed-clock";
		reg = <0>;
		#clock-cells = <0>;
		clock-frequency = <12000000>;
		};

		clk_32k: clock@1 {
		compatible = "fixed-clock";
		reg = <1>;
		#clock-cells = <0>;
		clock-frequency = <32768>;
		};
		};

		&tegra_car {
		clocks = <&clk_32k> <&osc>;
		};
		};

arch/arm/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -643,6 +643,7 @@ config ARCH_TEGRA
		select ARCH_HAS_CPUFREQ
		select CLKDEV_LOOKUP
		select CLKSRC_MMIO
		select CLKSRC_OF
		select COMMON_CLK
		select GENERIC_CLOCKEVENTS
		select GENERIC_GPIO

arch/arm/boot/dts/tegra20-paz00.dts

+2 −0

Original line number	Diff line number	Diff line
		@@ -266,6 +266,8 @@
		clock-frequency = <80000>;
		request-gpios = <&gpio 170 0>; /* gpio PV2 */
		slave-addr = <138>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		};

		i2c@7000d000 {

arch/arm/boot/dts/tegra20.dtsi

+50 −0

Original line number	Diff line number	Diff line
		@@ -9,6 +9,7 @@
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04 /* mpcore syncpt */
		0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;
		@@ -19,41 +20,49 @@
		compatible = "nvidia,tegra20-mpe";
		reg = <0x54040000 0x00040000>;
		interrupts = <0 68 0x04>;
		clocks = <&tegra_car 60>;
		};

		vi {
		compatible = "nvidia,tegra20-vi";
		reg = <0x54080000 0x00040000>;
		interrupts = <0 69 0x04>;
		clocks = <&tegra_car 100>;
		};

		epp {
		compatible = "nvidia,tegra20-epp";
		reg = <0x540c0000 0x00040000>;
		interrupts = <0 70 0x04>;
		clocks = <&tegra_car 19>;
		};

		isp {
		compatible = "nvidia,tegra20-isp";
		reg = <0x54100000 0x00040000>;
		interrupts = <0 71 0x04>;
		clocks = <&tegra_car 23>;
		};

		gr2d {
		compatible = "nvidia,tegra20-gr2d";
		reg = <0x54140000 0x00040000>;
		interrupts = <0 72 0x04>;
		clocks = <&tegra_car 21>;
		};

		gr3d {
		compatible = "nvidia,tegra20-gr3d";
		reg = <0x54180000 0x00040000>;
		clocks = <&tegra_car 24>;
		};

		dc@54200000 {
		compatible = "nvidia,tegra20-dc";
		reg = <0x54200000 0x00040000>;
		interrupts = <0 73 0x04>;
		clocks = <&tegra_car 27>, <&tegra_car 121>;
		clock-names = "disp1", "parent";

		rgb {
		status = "disabled";
		@@ -64,6 +73,8 @@
		compatible = "nvidia,tegra20-dc";
		reg = <0x54240000 0x00040000>;
		interrupts = <0 74 0x04>;
		clocks = <&tegra_car 26>, <&tegra_car 121>;
		clock-names = "disp2", "parent";

		rgb {
		status = "disabled";
		@@ -74,6 +85,8 @@
		compatible = "nvidia,tegra20-hdmi";
		reg = <0x54280000 0x00040000>;
		interrupts = <0 75 0x04>;
		clocks = <&tegra_car 51>, <&tegra_car 117>;
		clock-names = "hdmi", "parent";
		status = "disabled";
		};

		@@ -81,12 +94,14 @@
		compatible = "nvidia,tegra20-tvo";
		reg = <0x542c0000 0x00040000>;
		interrupts = <0 76 0x04>;
		clocks = <&tegra_car 102>;
		status = "disabled";
		};

		dsi {
		compatible = "nvidia,tegra20-dsi";
		reg = <0x54300000 0x00040000>;
		clocks = <&tegra_car 48>;
		status = "disabled";
		};
		};
		@@ -123,6 +138,12 @@
		0 42 0x04>;
		};

		tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
		};

		apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		@@ -142,6 +163,7 @@
		0 117 0x04
		0 118 0x04
		0 119 0x04>;
		clocks = <&tegra_car 34>;
		};

		ahb {
		@@ -183,6 +205,7 @@
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car 11>;
		status = "disabled";
		};

		@@ -191,6 +214,7 @@
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 18>;
		status = "disabled";
		};

		@@ -199,6 +223,7 @@
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		clocks = <&tegra_car 6>;
		status = "disabled";
		};

		@@ -207,6 +232,7 @@
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		clocks = <&tegra_car 96>;
		status = "disabled";
		};

		@@ -215,6 +241,7 @@
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		clocks = <&tegra_car 55>;
		status = "disabled";
		};

		@@ -223,6 +250,7 @@
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		clocks = <&tegra_car 65>;
		status = "disabled";
		};

		@@ -231,6 +259,7 @@
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		clocks = <&tegra_car 66>;
		status = "disabled";
		};

		@@ -238,6 +267,7 @@
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
		};

		rtc {
		@@ -252,6 +282,8 @@
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
		};

		@@ -262,6 +294,7 @@
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 43>;
		status = "disabled";
		};

		@@ -271,6 +304,8 @@
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
		};

		@@ -280,6 +315,8 @@
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
		};

		@@ -289,6 +326,8 @@
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
		};

		@@ -299,6 +338,7 @@
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
		};

		@@ -309,6 +349,7 @@
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
		};

		@@ -319,6 +360,7 @@
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
		};

		@@ -329,6 +371,7 @@
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
		};

		@@ -363,6 +406,7 @@
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>;
		status = "disabled";
		};

		@@ -371,6 +415,7 @@
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>;
		status = "disabled";
		};

		@@ -379,6 +424,7 @@
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;
		status = "disabled";
		};

		@@ -386,6 +432,7 @@
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
		};

		@@ -393,6 +440,7 @@
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
		};

		@@ -400,6 +448,7 @@
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
		};

		@@ -407,6 +456,7 @@
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
		};

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