Commit bd87c8fb authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'pm-cpufreq' 

* pm-cpufreq: (33 commits)
  cpufreq: imx6q: Fix imx6sx low frequency support
  cpufreq: speedstep-lib: make several arrays static, makes code smaller
  cpufreq: ti: Fix 'of_node_put' being called twice in error handling path
  cpufreq: dt-platdev: Drop few entries from whitelist
  cpufreq: dt-platdev: Automatically create cpufreq device with OPP v2
  ARM: ux500: don't select CPUFREQ_DT
  cpufreq: Convert to using %pOF instead of full_name
  cpufreq: Cap the default transition delay value to 10 ms
  cpufreq: dbx500: Delete obsolete driver
  mfd: db8500-prcmu: Get rid of cpufreq dependency
  cpufreq: enable the DT cpufreq driver on the Ux500
  cpufreq: Loongson2: constify platform_device_id
  cpufreq: dt: Add r8a7796 support to to use generic cpufreq driver
  cpufreq: remove setting of policy->cpu in policy->cpus during init
  cpufreq: mediatek: add support of cpufreq to MT7622 SoC
  cpufreq: mediatek: add cleanups with the more generic naming
  cpufreq: rcar: Add support for R8A7795 SoC
  cpufreq: dt: Add rk3328 compatible to use generic cpufreq driver
  cpufreq: s5pv210: add missing of_node_put()
  cpufreq: Allow dynamic switching with CPUFREQ_ETERNAL latency
  ...
parents 45a7953c fded5fc8

Documentation/admin-guide/pm/cpufreq.rst

+0 −8
Original line number Diff line number Diff line
@@ -479,14 +479,6 @@ This governor exposes the following tunables: 


	# echo `$(($(cat cpuinfo_transition_latency) * 750 / 1000)) > ondemand/sampling_rate





``min_sampling_rate``

	The minimum value of ``sampling_rate``.



	Equal to 10000 (10 ms) if :c:macro:`CONFIG_NO_HZ_COMMON` and

	:c:data:`tick_nohz_active` are both set or to 20 times the value of

	:c:data:`jiffies` in microseconds otherwise.



``up_threshold``

	If the estimated CPU load is above this value (in percent), the governor

	will set the frequency to the maximum value allowed for the policy.

Documentation/devicetree/bindings/clock/mt8173-cpu-dvfs.txt→Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

+247 −0
Original line number Diff line number Diff line 
Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC

Binding for MediaTek's CPUFreq driver

=====================================



Required properties:

- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
@@ -9,6 +10,8 @@ Required properties: 
			  transition and not stable yet.

	Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for

	generic clock consumer properties.

- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt

	for detail.

- proc-supply: Regulator for Vproc of CPU cluster.



Optional properties:
@@ -17,9 +20,166 @@ Optional properties: 
	       Vsram to fit SoC specific needs. When absent, the voltage scaling

	       flow is handled by hardware, hence no software "voltage tracking" is

	       needed.

- #cooling-cells:

- cooling-min-level:

- cooling-max-level:

	Please refer to Documentation/devicetree/bindings/thermal/thermal.txt

	for detail.



Example 1 (MT7623 SoC):



	cpu_opp_table: opp_table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-598000000 {

			opp-hz = /bits/ 64 <598000000>;

			opp-microvolt = <1050000>;

		};



		opp-747500000 {

			opp-hz = /bits/ 64 <747500000>;

			opp-microvolt = <1050000>;

		};



		opp-1040000000 {

			opp-hz = /bits/ 64 <1040000000>;

			opp-microvolt = <1150000>;

		};



		opp-1196000000 {

			opp-hz = /bits/ 64 <1196000000>;

			opp-microvolt = <1200000>;

		};



		opp-1300000000 {

			opp-hz = /bits/ 64 <1300000000>;

			opp-microvolt = <1300000>;

		};

	};



	cpu0: cpu@0 {

		device_type = "cpu";

		compatible = "arm,cortex-a7";

		reg = <0x0>;

		clocks = <&infracfg CLK_INFRA_CPUSEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table>;

		#cooling-cells = <2>;

		cooling-min-level = <0>;

		cooling-max-level = <7>;

	};

	cpu@1 {

		device_type = "cpu";

		compatible = "arm,cortex-a7";

		reg = <0x1>;

		operating-points-v2 = <&cpu_opp_table>;

	};

	cpu@2 {

		device_type = "cpu";

		compatible = "arm,cortex-a7";

		reg = <0x2>;

		operating-points-v2 = <&cpu_opp_table>;

	};

	cpu@3 {

		device_type = "cpu";

		compatible = "arm,cortex-a7";

		reg = <0x3>;

		operating-points-v2 = <&cpu_opp_table>;

	};



Example 2 (MT8173 SoC):

	cpu_opp_table_a: opp_table_a {

		compatible = "operating-points-v2";

		opp-shared;



		opp-507000000 {

			opp-hz = /bits/ 64 <507000000>;

			opp-microvolt = <859000>;

		};



		opp-702000000 {

			opp-hz = /bits/ 64 <702000000>;

			opp-microvolt = <908000>;

		};



		opp-1001000000 {

			opp-hz = /bits/ 64 <1001000000>;

			opp-microvolt = <983000>;

		};



		opp-1105000000 {

			opp-hz = /bits/ 64 <1105000000>;

			opp-microvolt = <1009000>;

		};



		opp-1183000000 {

			opp-hz = /bits/ 64 <1183000000>;

			opp-microvolt = <1028000>;

		};



		opp-1404000000 {

			opp-hz = /bits/ 64 <1404000000>;

			opp-microvolt = <1083000>;

		};



		opp-1508000000 {

			opp-hz = /bits/ 64 <1508000000>;

			opp-microvolt = <1109000>;

		};



		opp-1573000000 {

			opp-hz = /bits/ 64 <1573000000>;

			opp-microvolt = <1125000>;

		};

	};



	cpu_opp_table_b: opp_table_b {

		compatible = "operating-points-v2";

		opp-shared;



		opp-507000000 {

			opp-hz = /bits/ 64 <507000000>;

			opp-microvolt = <828000>;

		};



		opp-702000000 {

			opp-hz = /bits/ 64 <702000000>;

			opp-microvolt = <867000>;

		};



		opp-1001000000 {

			opp-hz = /bits/ 64 <1001000000>;

			opp-microvolt = <927000>;

		};



		opp-1209000000 {

			opp-hz = /bits/ 64 <1209000000>;

			opp-microvolt = <968000>;

		};



		opp-1404000000 {

			opp-hz = /bits/ 64 <1007000000>;

			opp-microvolt = <1028000>;

		};



		opp-1612000000 {

			opp-hz = /bits/ 64 <1612000000>;

			opp-microvolt = <1049000>;

		};



		opp-1807000000 {

			opp-hz = /bits/ 64 <1807000000>;

			opp-microvolt = <1089000>;

		};



		opp-1989000000 {

			opp-hz = /bits/ 64 <1989000000>;

			opp-microvolt = <1125000>;

		};

	};



Example:

--------

	cpu0: cpu@0 {

		device_type = "cpu";

		compatible = "arm,cortex-a53";
@@ -29,6 +189,7 @@ Example: 
		clocks = <&infracfg CLK_INFRA_CA53SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_a>;

	};



	cpu1: cpu@1 {
@@ -40,6 +201,7 @@ Example: 
		clocks = <&infracfg CLK_INFRA_CA53SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_a>;

	};



	cpu2: cpu@100 {
@@ -51,6 +213,7 @@ Example: 
		clocks = <&infracfg CLK_INFRA_CA57SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_b>;

	};



	cpu3: cpu@101 {
@@ -62,6 +225,7 @@ Example: 
		clocks = <&infracfg CLK_INFRA_CA57SEL>,

			 <&apmixedsys CLK_APMIXED_MAINPLL>;

		clock-names = "cpu", "intermediate";

		operating-points-v2 = <&cpu_opp_table_b>;

	};



	&cpu0 {

arch/arm/boot/dts/tango4-smp8758.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ 
			reg = <0>;

			clocks = <&clkgen CPU_CLK>;

			clock-latency = <1>;

			operating-points = <1215000 0 607500 0 405000 0 243000 0 135000 0>;

		};



		cpu1: cpu@1 {

drivers/cpufreq/Kconfig.arm

+8 −13
Original line number Diff line number Diff line
@@ -71,15 +71,6 @@ config ARM_HIGHBANK_CPUFREQ 


	  If in doubt, say N.



config ARM_DB8500_CPUFREQ

	tristate "ST-Ericsson DB8500 cpufreq" if COMPILE_TEST && !ARCH_U8500

	default ARCH_U8500

	depends on HAS_IOMEM

	depends on !CPU_THERMAL || THERMAL

	help

	  This adds the CPUFreq driver for ST-Ericsson Ux500 (DB8500) SoC

	  series.



config ARM_IMX6Q_CPUFREQ

	tristate "Freescale i.MX6 cpufreq support"

	depends on ARCH_MXC
@@ -96,14 +87,13 @@ config ARM_KIRKWOOD_CPUFREQ 
	  This adds the CPUFreq driver for Marvell Kirkwood

	  SoCs.



config ARM_MT8173_CPUFREQ

	tristate "Mediatek MT8173 CPUFreq support"

config ARM_MEDIATEK_CPUFREQ

	tristate "CPU Frequency scaling support for MediaTek SoCs"

	depends on ARCH_MEDIATEK && REGULATOR

	depends on ARM64 || (ARM_CPU_TOPOLOGY && COMPILE_TEST)

	depends on !CPU_THERMAL || THERMAL

	select PM_OPP

	help

	  This adds the CPUFreq driver support for Mediatek MT8173 SoC.

	  This adds the CPUFreq driver support for MediaTek SoCs.



config ARM_OMAP2PLUS_CPUFREQ

	bool "TI OMAP2+"
@@ -242,6 +232,11 @@ config ARM_STI_CPUFREQ 
	  this config option if you wish to add CPUFreq support for STi based

	  SoCs.



config ARM_TANGO_CPUFREQ

	bool

	depends on CPUFREQ_DT && ARCH_TANGO

	default y



config ARM_TEGRA20_CPUFREQ

	bool "Tegra20 CPUFreq support"

	depends on ARCH_TEGRA

drivers/cpufreq/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -53,12 +53,11 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o 


obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ)	+= brcmstb-avs-cpufreq.o

obj-$(CONFIG_ARCH_DAVINCI)		+= davinci-cpufreq.o

obj-$(CONFIG_ARM_DB8500_CPUFREQ)	+= dbx500-cpufreq.o

obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)	+= exynos5440-cpufreq.o

obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ)	+= highbank-cpufreq.o

obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o

obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ)	+= kirkwood-cpufreq.o

obj-$(CONFIG_ARM_MT8173_CPUFREQ)	+= mt8173-cpufreq.o

obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ)	+= mediatek-cpufreq.o

obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)	+= omap-cpufreq.o

obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2xx-cpufreq.o

obj-$(CONFIG_PXA3xx)			+= pxa3xx-cpufreq.o
@@ -75,6 +74,7 @@ obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o 
obj-$(CONFIG_ARM_SCPI_CPUFREQ)		+= scpi-cpufreq.o

obj-$(CONFIG_ARM_SPEAR_CPUFREQ)		+= spear-cpufreq.o

obj-$(CONFIG_ARM_STI_CPUFREQ)		+= sti-cpufreq.o

obj-$(CONFIG_ARM_TANGO_CPUFREQ)		+= tango-cpufreq.o

obj-$(CONFIG_ARM_TEGRA20_CPUFREQ)	+= tegra20-cpufreq.o

obj-$(CONFIG_ARM_TEGRA124_CPUFREQ)	+= tegra124-cpufreq.o

obj-$(CONFIG_ARM_TEGRA186_CPUFREQ)	+= tegra186-cpufreq.o

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