drm/amd/display: Add retry to read ddc_clock pin (bd4905a9) · Commits · 戴 / test

[WHY] On customer board, there is one pluse (1v , < 1ms) on DDC_CLK pin when plug / unplug DP cable. Driver will read it and config DP to HDMI/DVI dongle. [HOW] If there is a real dongle, DDC_CLK should be always pull high. Try to read again to recovery this special case. Retry times = 3. Need additional 3ms to detect DP passive dongle(3 failures) Signed-off-by:

Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:

Eric Yang <eric.yang2@amd.com> Acked-by:

Leo Li <sunpeng.li@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+17 −6

Original line number	Diff line number	Diff line
		@@ -342,7 +342,7 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
		{
		enum gpio_result gpio_result;
		uint32_t clock_pin = 0;

		uint8_t retry = 0;
		struct ddc *ddc;

		enum connector_id connector_id =
		@@ -371,11 +371,22 @@ bool dc_link_is_dp_sink_present(struct dc_link *link)
		return present;
		}

		/* Read GPIO: DP sink is present if both clock and data pins are zero */
		/* [anaumov] in DAL2, there was no check for GPIO failure */

		/*
		* Read GPIO: DP sink is present if both clock and data pins are zero
		*
		* [W/A] plug-unplug DP cable, sometimes customer board has
		* one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
		* then monitor can't br light up. Add retry 3 times
		* But in real passive dongle, it need additional 3ms to detect
		*/
		do {
		gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
		ASSERT(gpio_result == GPIO_RESULT_OK);
		if (clock_pin)
		udelay(1000);
		else
		break;
		} while (retry++ < 3);

		present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;

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