Commit bd371975 authored by Leon Romanovsky's avatar Leon Romanovsky
Browse files

net/mlx5: Update mlx5_ifc with DEVX UID bits 



Add DEVX information to WQ, SRQ, CQ, TIR, TIS, QP,
RQ, XRCD, PD, MKEY and MCG.

Each object that is created/destroyed/modified via verbs will
be stamped with a UID based on its user context. This is already
done for DEVX objects commands.

This will enable the firmware to enforce the usage of kernel objects
from the DEVX flow by validating that the same UID is used and the
resources are really related to the same user.

The addition of *_valid fields are needed to distinguish
how various addresses are passed.

For non-DEVX callers, all those fields will be zero.

Signed-off-by: default avatarLeon Romanovsky <leonro@mellanox.com>
parent 774ea6ee

include/linux/mlx5/mlx5_ifc.h

+43 −24
Original line number Original line Diff line number Diff line
@@ -1290,7 +1290,9 @@ struct mlx5_ifc_wq_bits { 
	u8         reserved_at_118[0x3];

	u8         reserved_at_118[0x3];

	u8         log_wq_sz[0x5];

	u8         log_wq_sz[0x5];





	u8         reserved_at_120[0x3];

	u8         dbr_umem_valid[0x1];

	u8         wq_umem_valid[0x1];

	u8         reserved_at_122[0x1];

	u8         log_hairpin_num_packets[0x5];

	u8         log_hairpin_num_packets[0x5];

	u8         reserved_at_128[0x3];

	u8         reserved_at_128[0x3];

	u8         log_hairpin_data_sz[0x5];

	u8         log_hairpin_data_sz[0x5];
@@ -2364,7 +2366,10 @@ struct mlx5_ifc_qpc_bits { 




	u8         dc_access_key[0x40];

	u8         dc_access_key[0x40];





	u8         reserved_at_680[0xc0];

	u8         reserved_at_680[0x3];

	u8         dbr_umem_valid[0x1];



	u8         reserved_at_684[0xbc];

};

};





struct mlx5_ifc_roce_addr_layout_bits {

struct mlx5_ifc_roce_addr_layout_bits {
@@ -2464,7 +2469,7 @@ struct mlx5_ifc_xrc_srqc_bits { 




	u8         wq_signature[0x1];

	u8         wq_signature[0x1];

	u8         cont_srq[0x1];

	u8         cont_srq[0x1];

	u8         reserved_at_22[0x1];

	u8         dbr_umem_valid[0x1];

	u8         rlky[0x1];

	u8         rlky[0x1];

	u8         basic_cyclic_rcv_wqe[0x1];

	u8         basic_cyclic_rcv_wqe[0x1];

	u8         log_rq_stride[0x3];

	u8         log_rq_stride[0x3];
@@ -3128,7 +3133,9 @@ enum { 




struct mlx5_ifc_cqc_bits {

struct mlx5_ifc_cqc_bits {

	u8         status[0x4];

	u8         status[0x4];

	u8         reserved_at_4[0x4];

	u8         reserved_at_4[0x2];

	u8         dbr_umem_valid[0x1];

	u8         reserved_at_7[0x1];

	u8         cqe_sz[0x3];

	u8         cqe_sz[0x3];

	u8         cc[0x1];

	u8         cc[0x1];

	u8         reserved_at_c[0x1];

	u8         reserved_at_c[0x1];
@@ -5314,7 +5321,7 @@ struct mlx5_ifc_modify_tis_bitmask_bits { 




struct mlx5_ifc_modify_tis_in_bits {

struct mlx5_ifc_modify_tis_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -5353,7 +5360,7 @@ struct mlx5_ifc_modify_tir_out_bits { 




struct mlx5_ifc_modify_tir_in_bits {

struct mlx5_ifc_modify_tir_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -5454,7 +5461,7 @@ struct mlx5_ifc_rqt_bitmask_bits { 




struct mlx5_ifc_modify_rqt_in_bits {

struct mlx5_ifc_modify_rqt_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -5641,7 +5648,10 @@ struct mlx5_ifc_modify_cq_in_bits { 




	struct mlx5_ifc_cqc_bits cq_context;

	struct mlx5_ifc_cqc_bits cq_context;





	u8         reserved_at_280[0x600];

	u8         reserved_at_280[0x40];



	u8         cq_umem_valid[0x1];

	u8         reserved_at_2c1[0x5bf];





	u8         pas[0][0x40];

	u8         pas[0][0x40];

};

};
@@ -5962,7 +5972,7 @@ struct mlx5_ifc_detach_from_mcg_out_bits { 




struct mlx5_ifc_detach_from_mcg_in_bits {

struct mlx5_ifc_detach_from_mcg_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6030,7 +6040,7 @@ struct mlx5_ifc_destroy_tis_out_bits { 




struct mlx5_ifc_destroy_tis_in_bits {

struct mlx5_ifc_destroy_tis_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6052,7 +6062,7 @@ struct mlx5_ifc_destroy_tir_out_bits { 




struct mlx5_ifc_destroy_tir_in_bits {

struct mlx5_ifc_destroy_tir_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6142,7 +6152,7 @@ struct mlx5_ifc_destroy_rqt_out_bits { 




struct mlx5_ifc_destroy_rqt_in_bits {

struct mlx5_ifc_destroy_rqt_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6507,7 +6517,7 @@ struct mlx5_ifc_dealloc_xrcd_out_bits { 




struct mlx5_ifc_dealloc_xrcd_in_bits {

struct mlx5_ifc_dealloc_xrcd_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6595,7 +6605,7 @@ struct mlx5_ifc_dealloc_pd_out_bits { 




struct mlx5_ifc_dealloc_pd_in_bits {

struct mlx5_ifc_dealloc_pd_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6674,7 +6684,9 @@ struct mlx5_ifc_create_xrc_srq_in_bits { 




	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;

	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;





	u8         reserved_at_280[0x600];

	u8         reserved_at_280[0x40];

	u8         xrc_srq_umem_valid[0x1];

	u8         reserved_at_2c1[0x5bf];





	u8         pas[0][0x40];

	u8         pas[0][0x40];

};

};
@@ -6693,7 +6705,7 @@ struct mlx5_ifc_create_tis_out_bits { 




struct mlx5_ifc_create_tis_in_bits {

struct mlx5_ifc_create_tis_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6717,7 +6729,7 @@ struct mlx5_ifc_create_tir_out_bits { 




struct mlx5_ifc_create_tir_in_bits {

struct mlx5_ifc_create_tir_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6823,7 +6835,7 @@ struct mlx5_ifc_create_rqt_out_bits { 




struct mlx5_ifc_create_rqt_in_bits {

struct mlx5_ifc_create_rqt_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -6908,7 +6920,10 @@ struct mlx5_ifc_create_qp_in_bits { 




	struct mlx5_ifc_qpc_bits qpc;

	struct mlx5_ifc_qpc_bits qpc;





	u8         reserved_at_800[0x80];

	u8         reserved_at_800[0x60];



	u8         wq_umem_valid[0x1];

	u8         reserved_at_861[0x1f];





	u8         pas[0][0x40];

	u8         pas[0][0x40];

};

};
@@ -6970,7 +6985,8 @@ struct mlx5_ifc_create_mkey_in_bits { 
	u8         reserved_at_40[0x20];

	u8         reserved_at_40[0x20];





	u8         pg_access[0x1];

	u8         pg_access[0x1];

	u8         reserved_at_61[0x1f];

	u8         mkey_umem_valid[0x1];

	u8         reserved_at_62[0x1e];





	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;

	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
@@ -7173,7 +7189,10 @@ struct mlx5_ifc_create_cq_in_bits { 




	struct mlx5_ifc_cqc_bits cq_context;

	struct mlx5_ifc_cqc_bits cq_context;





	u8         reserved_at_280[0x600];

	u8         reserved_at_280[0x60];



	u8         cq_umem_valid[0x1];

	u8         reserved_at_2e1[0x59f];





	u8         pas[0][0x40];

	u8         pas[0][0x40];

};

};
@@ -7221,7 +7240,7 @@ struct mlx5_ifc_attach_to_mcg_out_bits { 




struct mlx5_ifc_attach_to_mcg_in_bits {

struct mlx5_ifc_attach_to_mcg_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -7348,7 +7367,7 @@ struct mlx5_ifc_alloc_xrcd_out_bits { 




struct mlx5_ifc_alloc_xrcd_in_bits {

struct mlx5_ifc_alloc_xrcd_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];
@@ -7436,7 +7455,7 @@ struct mlx5_ifc_alloc_pd_out_bits { 




struct mlx5_ifc_alloc_pd_in_bits {

struct mlx5_ifc_alloc_pd_in_bits {

	u8         opcode[0x10];

	u8         opcode[0x10];

	u8         reserved_at_10[0x10];

	u8         uid[0x10];





	u8         reserved_at_20[0x10];

	u8         reserved_at_20[0x10];

	u8         op_mod[0x10];

	u8         op_mod[0x10];

CRA Git | Maintained and supported by SUSTech CRA and CCSE