Commit bd1be8e8 authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: A few more color indentation changes 



Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a696dc20

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

+15 −18
Original line number Diff line number Diff line
@@ -135,16 +135,14 @@ static void dce_ipp_cursor_set_attributes( 
}





static void dce_ipp_program_prescale(

	struct input_pixel_processor *ipp,

static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,

				     struct ipp_prescale_params *params)

{

	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);



	/* set to bypass mode first before change */

	REG_UPDATE(PRESCALE_GRPH_CONTROL,

		GRPH_PRESCALE_BYPASS,

		1);

		   GRPH_PRESCALE_BYPASS, 1);



	REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,

		  GRPH_PRESCALE_SCALE_R, params->scale,
@@ -223,8 +221,7 @@ static void dce_ipp_set_degamma( 
	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);

	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;



	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS ||

			mode == IPP_DEGAMMA_MODE_HW_sRGB);

	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);



	REG_SET_3(DEGAMMA_CONTROL, 0,

		  GRPH_DEGAMMA_MODE, degamma_type,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

+2 −3
Original line number Diff line number Diff line
@@ -1177,8 +1177,7 @@ void dce110_opp_set_csc_default( 
		default_adjust->out_color_space);

}



static void program_pwl(

	struct dce_transform *xfm_dce,

static void program_pwl(struct dce_transform *xfm_dce,

			const struct pwl_params *params)

{

	int retval;

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+27 −52
Original line number Diff line number Diff line
@@ -307,8 +307,7 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, 
	return result;

}



static bool convert_to_custom_float(

		struct pwl_result_data *rgb_resulted,

static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,

				    struct curve_points *arr_points,

				    uint32_t hw_points_num)

{
@@ -322,25 +321,19 @@ static bool convert_to_custom_float( 
	fmt.mantissa_bits = 12;

	fmt.sign = true;



	if (!convert_to_custom_float_format(

		arr_points[0].x,

		&fmt,

	if (!convert_to_custom_float_format(arr_points[0].x, &fmt,

					    &arr_points[0].custom_float_x)) {

		BREAK_TO_DEBUGGER();

		return false;

	}



	if (!convert_to_custom_float_format(

		arr_points[0].offset,

		&fmt,

	if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,

					    &arr_points[0].custom_float_offset)) {

		BREAK_TO_DEBUGGER();

		return false;

	}



	if (!convert_to_custom_float_format(

		arr_points[0].slope,

		&fmt,

	if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,

					    &arr_points[0].custom_float_slope)) {

		BREAK_TO_DEBUGGER();

		return false;
@@ -349,25 +342,19 @@ static bool convert_to_custom_float( 
	fmt.mantissa_bits = 10;

	fmt.sign = false;



	if (!convert_to_custom_float_format(

		arr_points[1].x,

		&fmt,

	if (!convert_to_custom_float_format(arr_points[1].x, &fmt,

					    &arr_points[1].custom_float_x)) {

		BREAK_TO_DEBUGGER();

		return false;

	}



	if (!convert_to_custom_float_format(

		arr_points[1].y,

		&fmt,

	if (!convert_to_custom_float_format(arr_points[1].y, &fmt,

					    &arr_points[1].custom_float_y)) {

		BREAK_TO_DEBUGGER();

		return false;

	}



	if (!convert_to_custom_float_format(

		arr_points[2].slope,

		&fmt,

	if (!convert_to_custom_float_format(arr_points[2].slope, &fmt,

					    &arr_points[2].custom_float_slope)) {

		BREAK_TO_DEBUGGER();

		return false;
@@ -377,49 +364,37 @@ static bool convert_to_custom_float( 
	fmt.sign = true;



	while (i != hw_points_num) {

		if (!convert_to_custom_float_format(

			rgb->red,

			&fmt,

		if (!convert_to_custom_float_format(rgb->red, &fmt,

						    &rgb->red_reg)) {

			BREAK_TO_DEBUGGER();

			return false;

		}



		if (!convert_to_custom_float_format(

			rgb->green,

			&fmt,

		if (!convert_to_custom_float_format(rgb->green, &fmt,

						    &rgb->green_reg)) {

			BREAK_TO_DEBUGGER();

			return false;

		}



		if (!convert_to_custom_float_format(

			rgb->blue,

			&fmt,

		if (!convert_to_custom_float_format(rgb->blue, &fmt,

						    &rgb->blue_reg)) {

			BREAK_TO_DEBUGGER();

			return false;

		}



		if (!convert_to_custom_float_format(

			rgb->delta_red,

			&fmt,

		if (!convert_to_custom_float_format(rgb->delta_red, &fmt,

						    &rgb->delta_red_reg)) {

			BREAK_TO_DEBUGGER();

			return false;

		}



		if (!convert_to_custom_float_format(

			rgb->delta_green,

			&fmt,

		if (!convert_to_custom_float_format(rgb->delta_green, &fmt,

						    &rgb->delta_green_reg)) {

			BREAK_TO_DEBUGGER();

			return false;

		}



		if (!convert_to_custom_float_format(

			rgb->delta_blue,

			&fmt,

		if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,

						    &rgb->delta_blue_reg)) {

			BREAK_TO_DEBUGGER();

			return false;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

+2 −2
Original line number Diff line number Diff line
@@ -213,8 +213,8 @@ static void dpp1_cm_set_regamma_pwl( 
		else

			dpp1_cm_program_regamma_lutb_settings(dpp_base, params);



		dpp1_cm_program_regamma_lut(

				dpp_base, params->rgb_resulted, params->hw_points_num);

		dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,

					    params->hw_points_num);

		dpp->pwl_data = *params;



		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

+11 −14
Original line number Diff line number Diff line
@@ -365,34 +365,31 @@ void dpp1_cm_set_output_csc_adjustment( 
	dpp1_cm_program_color_matrix(dpp, tbl_entry);

}



void dpp1_cm_power_on_regamma_lut(

	struct dpp *dpp_base,

void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,

				  bool power_on)

{

	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);



	REG_SET(CM_MEM_PWR_CTRL, 0,

		RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);



}



void dpp1_cm_program_regamma_lut(

		struct dpp *dpp_base,

void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,

				 const struct pwl_result_data *rgb,

				 uint32_t num)

{

	uint32_t i;

	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);



	for (i = 0 ; i < num; i++) {

		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);

		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);

		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);



		REG_SET(CM_RGAM_LUT_DATA, 0,

				CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);

		REG_SET(CM_RGAM_LUT_DATA, 0,

				CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);

		REG_SET(CM_RGAM_LUT_DATA, 0,

				CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);

		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);

		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);

		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);



	}

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