Commit bd067f83 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Michael Ellerman
Browse files

powerpc/64: Fix naming of cache block vs. cache line 



In a number of places we called "cache line size" what is actually
the cache block size, which in the powerpc architecture, means the
effective size to use with cache management instructions (it can
be different from the actual cache line size).

We fix the naming across the board and properly retrieve both
pieces of information when available in the device-tree.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent f9e473f1

arch/powerpc/include/asm/cache.h

+7 −5
Original line number Diff line number Diff line
@@ -33,12 +33,14 @@ 
struct ppc64_caches {

	u32	dsize;			/* L1 d-cache size */

	u32	dline_size;		/* L1 d-cache line size	*/

	u32	log_dline_size;

	u32	dlines_per_page;

	u32	dblock_size;		/* L1 d-cache block size */

	u32	log_dblock_size;

	u32	dblocks_per_page;

	u32	isize;			/* L1 i-cache size */

	u32	iline_size;		/* L1 i-cache line size	*/

	u32	log_iline_size;

	u32	ilines_per_page;

	u32	iline_size;		/* L1 d-cache line size	*/

	u32	iblock_size;		/* L1 i-cache block size */

	u32	log_iblock_size;

	u32	iblocks_per_page;

};



extern struct ppc64_caches ppc64_caches;

arch/powerpc/include/asm/page_64.h

+2 −2
Original line number Diff line number Diff line
@@ -47,14 +47,14 @@ static inline void clear_page(void *addr) 
	unsigned long iterations;

	unsigned long onex, twox, fourx, eightx;



	iterations = ppc64_caches.dlines_per_page / 8;

	iterations = ppc64_caches.dblocks_per_page / 8;



	/*

	 * Some verisions of gcc use multiply instructions to

	 * calculate the offsets so lets give it a hand to

	 * do better.

	 */

	onex = ppc64_caches.dline_size;

	onex = ppc64_caches.dblock_size;

	twox = onex << 1;

	fourx = onex << 2;

	eightx = onex << 3;

arch/powerpc/kernel/align.c

+1 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr) 
	int i, size;



#ifdef __powerpc64__

	size = ppc64_caches.dline_size;

	size = ppc64_caches.dblock_size;

#else

	size = L1_CACHE_BYTES;

#endif

arch/powerpc/kernel/asm-offsets.c

+6 −6
Original line number Diff line number Diff line
@@ -163,12 +163,12 @@ int main(void) 
	DEFINE(TI_CPU, offsetof(struct thread_info, cpu));



#ifdef CONFIG_PPC64

	DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size));

	DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size));

	DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page));

	DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size));

	DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size));

	DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page));

	DEFINE(DCACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, dblock_size));

	DEFINE(DCACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, log_dblock_size));

	DEFINE(DCACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, dblocks_per_page));

	DEFINE(ICACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, iblock_size));

	DEFINE(ICACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, log_iblock_size));

	DEFINE(ICACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, iblocks_per_page));

	/* paca */

	DEFINE(PACA_SIZE, sizeof(struct paca_struct));

	DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index));

arch/powerpc/kernel/misc_64.S

+14 −14
Original line number Diff line number Diff line
@@ -80,12 +80,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 
 * each other.

 */

 	ld	r10,PPC64_CACHES@toc(r2)

	lwz	r7,DCACHEL1LINESIZE(r10)/* Get cache line size */

	lwz	r7,DCACHEL1BLOCKSIZE(r10)/* Get cache block size */

	addi	r5,r7,-1

	andc	r6,r3,r5		/* round low to line bdy */

	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5		/* ensure we get enough */

	lwz	r9,DCACHEL1LOGLINESIZE(r10)	/* Get log-2 of cache line size */

	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of cache block size */

	srw.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	mtctr	r8
@@ -96,12 +96,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 


/* Now invalidate the instruction cache */

	

	lwz	r7,ICACHEL1LINESIZE(r10)	/* Get Icache line size */

	lwz	r7,ICACHEL1BLOCKSIZE(r10)	/* Get Icache block size */

	addi	r5,r7,-1

	andc	r6,r3,r5		/* round low to line bdy */

	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5

	lwz	r9,ICACHEL1LOGLINESIZE(r10)	/* Get log-2 of Icache line size */

	lwz	r9,ICACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of Icache block size */

	srw.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	mtctr	r8
@@ -128,12 +128,12 @@ _GLOBAL(flush_dcache_range) 
 * Different systems have different cache line sizes

 */

 	ld	r10,PPC64_CACHES@toc(r2)

	lwz	r7,DCACHEL1LINESIZE(r10)	/* Get dcache line size */

	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */

	addi	r5,r7,-1

	andc	r6,r3,r5		/* round low to line bdy */

	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5		/* ensure we get enough */

	lwz	r9,DCACHEL1LOGLINESIZE(r10)	/* Get log-2 of dcache line size */

	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of dcache block size */

	srw.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	mtctr	r8
@@ -156,12 +156,12 @@ EXPORT_SYMBOL(flush_dcache_range) 
 */

_GLOBAL(flush_dcache_phys_range)

 	ld	r10,PPC64_CACHES@toc(r2)

	lwz	r7,DCACHEL1LINESIZE(r10)	/* Get dcache line size */

	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */

	addi	r5,r7,-1

	andc	r6,r3,r5		/* round low to line bdy */

	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5		/* ensure we get enough */

	lwz	r9,DCACHEL1LOGLINESIZE(r10)	/* Get log-2 of dcache line size */

	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of dcache block size */

	srw.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	mfmsr	r5			/* Disable MMU Data Relocation */
@@ -184,12 +184,12 @@ _GLOBAL(flush_dcache_phys_range) 


_GLOBAL(flush_inval_dcache_range)

 	ld	r10,PPC64_CACHES@toc(r2)

	lwz	r7,DCACHEL1LINESIZE(r10)	/* Get dcache line size */

	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */

	addi	r5,r7,-1

	andc	r6,r3,r5		/* round low to line bdy */

	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5		/* ensure we get enough */

	lwz	r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */

	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */

	srw.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	sync
@@ -225,8 +225,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 
/* Flush the dcache */

 	ld	r7,PPC64_CACHES@toc(r2)

	clrrdi	r3,r3,PAGE_SHIFT           	    /* Page align */

	lwz	r4,DCACHEL1LINESPERPAGE(r7)	/* Get # dcache lines per page */

	lwz	r5,DCACHEL1LINESIZE(r7)		/* Get dcache line size */

	lwz	r4,DCACHEL1BLOCKSPERPAGE(r7)	/* Get # dcache blocks per page */

	lwz	r5,DCACHEL1BLOCKSIZE(r7)	/* Get dcache block size */

	mr	r6,r3

	mtctr	r4

0:	dcbst	0,r6
@@ -236,8 +236,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 


/* Now invalidate the icache */	



	lwz	r4,ICACHEL1LINESPERPAGE(r7)	/* Get # icache lines per page */

	lwz	r5,ICACHEL1LINESIZE(r7)		/* Get icache line size */

	lwz	r4,ICACHEL1BLOCKSPERPAGE(r7)	/* Get # icache blocks per page */

	lwz	r5,ICACHEL1BLOCKSIZE(r7)	/* Get icache block size */

	mtctr	r4

1:	icbi	0,r3

	add	r3,r3,r5

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